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United States Utility Patents
6,536,020 - 6,536,029
Previous 10 Next 10
| Number | | Title |
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6,536,020 |
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Efficient generation of optimum test data |
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6,536,021 |
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Method and system for representing hierarchical extracted resistance-capacitance files of a circuit model |
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6,536,022 |
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Two pole coupling noise analysis model for submicron integrated circuit design verification |
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6,536,023 |
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Method and system for hierarchical metal-end, enclosure and exposure checking |
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6,536,024 |
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Method for making integrated circuits having gated clock trees |
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6,536,025 |
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Receiver deskewing of multiple source synchronous bits from a parallel bus |
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6,536,026 |
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Method and apparatus for analyzing small signal response and noise in nonlinear circuits |
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6,536,027 |
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Cell pin extensions for integrated circuits |
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6,536,028 |
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Standard block architecture for integrated circuit design |
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6,536,029 |
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Programmable logic controller method, system and apparatus |
For U.S. patent law, rules, and procedures see MPEP.
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