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United States Utility Patents
6,204,120 - 6,204,129
Previous 10 Next 10
| Number | | Title |
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6,204,120 |
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Semiconductor wafer pretreatment utilizing ultraviolet activated chlorine |
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6,204,121 |
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Method for bottom electrode of capacitor |
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6,204,122 |
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Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios |
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6,204,123 |
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Vertical floating gate transistor with epitaxial channel |
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6,204,124 |
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Method for forming high density nonvolatile memories with high capacitive-coupling ratio |
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6,204,125 |
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Method of forming a gate in a stack gate flash EEPROM cell |
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6,204,126 |
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Method to fabricate a new structure with multi-self-aligned for split-gate flash |
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6,204,127 |
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Method of manufacturing bit lines in memory |
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6,204,128 |
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Method for fabricating semiconductor device |
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6,204,129 |
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Method for producing a high-voltage and low-voltage MOS transistor with salicide structure |
For U.S. patent law, rules, and procedures see MPEP.
Disclaimer. Information presented on this page while believed to be reliable, is provided "as is" with no warranties of its accuracy or timeliness. For legal advice seek help of a licensed professional.
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