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Home | Alpha Telephone | Domain Names | Web Hosting | Get Traffic | xrEvidence | xrSoccer United States Patent
Semiconductor memory device A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.
Primary Examiner: Fears; Terrell W. Attorney, Agent or Firm: This application is a division of application Ser. No. 07/869,917 filed Apr. 15, 1992 pending. What is claimed is: 1. A semiconductor memory device, comprising: a first memory cell array including a plurality of memory cells arranged in a matrix of rows and columns; a second memory cell array including a plurality of memory cells arranged in a matrix of rows and columns; first address means for generating a first internal address signal for designating a row and a column of said first memory array in accordance with an externally applied address; and second address means responsive to an externally applied address for generating a second internal address signal for designating a row and a column of said second memory cell array; wherein said first and second address means are activated in synchronization with an externally applied clock signal and operates simultaneously for generating said first internal address and said second internal address simultaneously. 2. A semiconductor memory device according to claim 1, wherein, said first address means includes a first row address means in response to an external first row address for generating a first internal row address designating a row of memory cells of the first memory array and a first column address means responsive to an external first column address for generating a first internal column address for designating a column of memory cells of the first memory array, and said second address means includes a second row address means responsive to an external second row address for generating a second internal row address for designating a row of memory cells of the second memory array and a second column address means responsive to an external second column address for designating a column of memory cells of the second memory array, and wherein said first column address means is shared in part with said second row and column address means. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices and, specifically, to a clock synchronized type semiconductor memory device which operates in synchronization with externally applied clock signals. More specifically, the present invention relates to a structure of a semiconductor memory device containing a cache, in which a dynamic random access memory (DRAM) having a large storage capacity serving as a main memory, and a static random access memory (SRAM) having small storage capacity serving as a cache memory are integrated on the same semiconductor chip. 2. Description of the Background Art Historical Review on Memory Environment in a Conventional Data Processing System (i) Usage of standard DRAM as a main memory Operation speed of recent 16-bit or 32-bit microprocessing unit (MPU) has been so much increased as to have operation clock frequency as high as 25MHz or higher. In a data processing system, a standard DRAM (Dynamic Random Access Memory) is often used as a main memory having large storage capacity, since cost per bit is low. Although access time in the standard DRAM has been reduced, the speed of operation of the MPU has been increased much faster than that of the standard DRAM. Consequently, in a data processing system using the standard DRAM as a main memory, increase of wait state is inevitable. The gap in speed of operation between MPU and the standard DRAM is inevitable because the standard DRAM has the following characteristics. (1) A row address and a column address are time divisionally multiplexed and applied to the same address pin terminals. The row address is taken in the device at a falling edge of a row address strobe signal/RAS. The column address is taken in the device at a falling edge of a column address strobe signal/CAS. The row address strobe signal/RAS defines start of a memory cycle and activates row selecting circuitry. The column address strobe signal/CAS activates column selecting circuitry. Since a prescribed time period called "RAS-CAS delay time (tRCD)" is necessary from the time the signal/RAS is set to an active state to the time the signal/CAS is set to the active state, there is a limit in reducing the access time, namely, there is a limit derived from address multiplexing. (2) When the row address strobe signal/RAS is once raised to set the DRAM to a standby state, the row address strobe signal/RAS cannot fall to "L" again until a time period called a RAS precharge time (tRP) has lapsed. The RAS precharge time is necessary for surely precharging various signal lines in the DRAM to predetermined potentials. Due to the RAS precharge time TRP, the cycle time of DRAM cannot be reduced. In addition, when the cycle time of the DRAM is reduced, the number of charging/discharging of signal lines in the DRAM is increased, which increases current consumption. (3) The higher speed of operation of the DRAM can be realized by circuit technique such as improvement of layout, increase of degree of integration of circuits, development in process technique and by applicational improvement such as improvement in the method of driving. However, the speed of operation of the MPU is increased at much faster rate than DRAM. The speed of operation of semiconductor memories is hierarchical. For example, there are high speed bipolar RAMs using bipolar transistors such as ECLRAMs (Emitter Coupled RAM) and Static RAM, and relatively low speed DRAMs using MOS transistors (insulated gate type field effect transistors). It is very difficult to expect the operation speed (cycle time) as fast as several tens ns (nano seconds) in a standard DRAM formed of MOS transistors. There have been various applicational improvements to stop the gap between speed of operations of the MPU and the standard DRAM. Such improvements mainly comprise the following two approaches. (1) Use of high speed mode of the DRAM and interleave method (2) External provision of a high speed cache memory (SRAM). The first approach (1) includes a method of using a high speed mode such as a static column mode or a page mode, and a method of combining the high speed mode and the interleave method. In the static column mode, one word line (one row) is selected, and thereafter only the column address is changed successively, to successively access memory cells of this row. In the page mode, one word line is selected, and then column addresses are successively taken by toggling the signal/GAS to successively access memory cells connected to the selected one word line. In either of these modes, memory cells can be accessed without toggling the signal/RAS, enabling higher speed accessing than the normal access using the signals/RAS and/GAS. In the interleave method, a plurality of memories are provided in parallel to a data bus, and by alternately or successively accessing the plurality of memories, the access time is reduced in effect. The use of high speed mode of the DRAM and combination of the high speed mode and the interleave method have been known as a method of using the standard DRAM as a high speed DRAM in a simple and relatively effective manner. The second approach (2) has been widely used in a main frame art. A high speed cache memory is expensive. However, in the field of personal computers in which high performance as well as low cost are desired, this approach is employed in some parts of the field with a sacrifice of cost. There are three possible ways to provide the high speed cache memory. Namely, (a) the high speed cache memory is contained in the MPU itself; (b) the high speed cache memory is provided outside the MPU; and (c) the high speed cache memory is not separately provided but the high speed mode contained in the standard DRAM is used as a cache (the high speed mode is used as a pseudo cache memory). When a cache hit occurs, the standard DRAM is accessed in the high speed mode, and at the time of a cache miss, the standard DRAM is accessed in the normal mode. The above mentioned three ways (a) to (c) have been employed in the data processing systems in some way or other. In most MPU systems, the memories are organized in a bank structure and interleaving is carried out on bank by bank basis in order to conceal the RAS precharge time (TRP) which is inevitable in the DRAM, in view of cost. By this method, the cycle time of the DRAM can be substantially one half that of the specification value. The method of interleave is effective only when memories are sequentially accessed. When the same memory bank is to be continuously accessed, it is ineffective. Further, substantial improvement of the access time of the DRAM itself cannot be realized. The minimum unit of the memory must be at least 2 banks. When the high speed mode such as the page mode or the static column mode is used, the access time can be reduced effectively only when the MPU successively accesses a certain page (data of a designated one row). This method is effective to some extent when the number of banks is comparatively large, for example 2 to 4, since different rows can be accessed in different banks. When the data of the memory requested by the MPU does not exist in the given page, it is called a "miss hit" (cache miss). Normally, a group of data are stored in adjacent addresses or sequential addresses. In the high speed mode, a row address, which is one half of the addresses, has been already designated, and therefore possibility of "miss hit" is high. When the number of banks becomes as large as 30 to 40, data of different pages can be stored in different banks, and therefore the "miss hit" rate is remarkably reduced. However, it is not practical to provide 30 to 40 banks in a data processing system. In addition, if a "miss hit" occurs, the signal/RAS is raised and the DRAM must be returned to the precharge cycle in order to reselect the row address, which sacrifices the characteristic of the bank structure. In the above described second method (2), a high speed cache memory is provided between the MPU and the standard DRAM. In this case, the standard DRAM may have relatively low speed of operation. Standard DRAMs having storage capacities as large as 4M bits or 16M bits have come to be used. In a small system such as a personal computer, the main memory thereof can be formed by one or several chips of standard DRAMs. External provision of the high speed cache memory is not so effective in such a small system in which the main memory can be formed of one standard DRAM. If the standard DRAM is used as the main memory, the data transfer speed between the high speed cache memory and the main memory is limited by the number of data input/output terminals of the standard DRAM, which constitutes a bottleneck in increasing the speed of the system. When the high speed mode is used as a pseudo cache memory, the speed of operation thereof is slower than the high speed cache memory, and it is difficult to realize the desired system performance. (ii) Consideration on a conventional cache containing DRAM Provision of the high speed cache memory (SRAM) in the DRAM is proposed as a method of forming a relatively inexpensive and small system, which can solve the problem of sacrifice of system performance when the interleave method or the high speed operation mode is used. More specifically, a single chip memory having a hierarchical structure of a DRAM serving as a main memory and a SRAM serving as a cache memory has been conceived. The one-chip memory having such a hierarchical structure is called a cache DRAM (CDRAM). The CDRAM will be described with reference to FIGS. 1 through 4. FIG. 1 shows a structure of a main portion of a conventional standard 1 megabit DRAM. As shown in FIG. 1, the DRAM comprises a memory cell array 500 including a plurality of memory cells MC arranged in a matrix of rows and columns. A row of memory cells are connected to one word line WL. A column of memory cells MC are connected to one column line CL. Normally, the column line CL is formed by a pair of bit lines. A memory cell MC is positioned at a crossing of one of the pair of bit lines and one word line WL. In a 1M DRAM, the memory cells MC are arranged in a matrix of 1024 rows.times.1024 columns. Namely, the memory cell array 500 includes 1024 word lines WLs and 1024 column lines CLs (1024 pairs of bit lines). The DRAM further comprises a row decoder 502 which decodes an externally applied row address (not shown) for selecting a corresponding row of the memory cell array 500; a sense amplifier which detects and amplifies data of the memory cell connected to the word line selected by the row decoder 502; and a column decoder which decodes an externally applied column address (not shown) for selecting a corresponding column of the memory cell array 502. In FIG. 1, the sense amplifier and the column decoder are denoted by one block 504. If the DRAM has a .times.1 bit structure in which input/output of data is effected bit by bit, one column line CL (a bit line pair) is selected by the column decoder. If the DRAM has a .times.4 bit structure in which input/output of data is effected 4 bits by 4 bits, 4 column lines CL are selected by the column decoder. One sense amplifier is provided for each column line (bit line pair) CL in the block 504. In memory access for writing data to or reading data from the memory cell MC in the DRAM, the following operation is carried out. First, a row address is applied to the row decoder 502. The row decoder 502 decodes the row address and raises the potential of one word line WL in the memory cell array 500 to "H". Data of the 1024 bits of memory cells MC connected to the selected word line WL are transmitted to corresponding column lines CL. The data on the column lines CL are amplified by sense amplifiers included in the block 504. Selection of a memory cell to which the data is written or from which the data is read out of the memory cells connected to the selected word line WL is carried out by a column selection signal from the column decoder included in the block 504. The column decoder decodes column address signals (more accurately, internal column address signals), and generates a column selecting signal for selecting the corresponding column in the memory cell array 500. In the above described high speed mode, column addresses are successively applied to the column decoder included in the block 504. In the static column mode operation, column addresses applied at predetermined time intervals are decoded as new column addresses by the column decoder, and the corresponding memory cell out of the memory cells connected to the selected word line WL is selected by the column line CL. In the page mode, new column address is applied at every toggling of the signal /CAS, and the column decoder decodes the column address to select the corresponding column line. In this manner, one row of memory cells MC connected to the selected word line WL can be accessed at high speed by setting one word line WL at a selected state and by changing the column addresses only. FIG. 2 shows a general structure of a conventional 1M bit CDRAM. Referring to FIG. 2, the conventional CDRAM comprises, in addition to the components of the standard DRAM shown in FIG. 1, SRAM 506 and a transfer gate 508 for transferring data between one row of the memory cell array 500 of the DRAM and the SRAM 506. The SRAM includes a cache register provided corresponding to each column line CL of the memory cell array 500 so as to enable simultaneous storage of data of one row of the DRAM memory cell array 500. Therefore, 1024 cache registers are provided. The cache register is formed by a static memory cell (SRAM cell). In the structure of the CDRAM shown in FIG. 2, when a signal representing a cache hit is externally applied, the SRAM 506 is accessed, enabling access to the memory at high speed. At the time of a cache miss (miss hit), the DRAM portion is accessed. A CDRAM as described above having a DRAM of a large storage capacity and a high speed SRAM integrated on the same chip is disclosed in, for example, Japanese Patent Laying-Open Nos. 60-7690 and 62-38590. In the above described conventional CDRAM structure, column lines (bit line pairs) CL of the DRAM memory cell array 500 and column lines (bit line pairs) of the SRAM (cache memory) 506 are connected in one to one correspondence through a transfer gate 508. More specifically, in the above described conventional CDRAM structure, data of the memory cells connected to one word line WL in the DRAM memory cell array 500 and the data of the same number of SRAM cells as memory cells of one row of the memory cell array 500 are transferred bi-directionally and simultaneously, through the transfer gate 508. In this structure, the SRAM 506 is used as a cache memory and the DRAM is used as a main memory. The so called block size of the cache is considered to be the number of bits (memory cells) the contents of which are rewritten in one data transfer in SRAM 506. Therefore, the block size is the same as the number of memory cells which are physically coupled to one word line WL of DRAM memory cell array 500. As shown in FIGS. 1 and 2, when 1024 memory cells are physically connected to one word line WL, the block size is 1024. Generally, when the block size becomes larger, the hit rate is increased. However, if the cache memory has the same size, the number of sets is reduced in inverse proportion to the block size, and therefore the hit rate is decreased. For example, when the cache size is 4K bits and the block size 1024, the number of sets is 4. However, if the block size is 32, the number of sets is 128. Therefore, in the conventional CDRAM structure, the block size is made too large, and the cache hit rate cannot be very much improved. A structure enabling reduction in block size is disclosed in, for example, Japanese Patent Laying-Open No. 1-146187. In this prior art, column lines (bit line pairs) of the DRAM array and the SRAM array are arranged in one to one correspondence, but they are divided into a plurality of blocks in the column direction. Selection of the block is carried out by a block decoder. At the time of a cache miss (miss hit), one block is selected by the block decoder. Data are transferred only between the selected DRAM block and the associated SRAM block. By this structure, the block size of the cache memory can be reduced to an appropriate size. However, there remains the following problem unsolved. FIG. 3 shows a standard array structure of a 1M bit DRAM array. In FIG. 3, the DRAM array is divided into 8 memory blocks DMB1 to DMB8. A row decoder 502 is commonly provided for the memory blocks DMB1 to DMB8 on one side in the longitudinal direction of the memory array. For each of the memory blocks DMB1 to DMB8, (sense amplifier+column decoder) blocks 504-1 to 504-8 are provided. Each of the memory blocks DMB1 to DMB8 has the capacity of 128K bits. In FIG. 3, one memory block DMB is shown to have 128 rows and 1024 columns, as an example. One column line CL includes a pair of bit lines BL, /BL. As shown in FIG. 3, when the DRAM memory cell array is divided into a plurality of blocks, one bit line BL (and/BL) becomes shorter. In data reading, charges stored in a capacitor (memory cell capacitor) in the memory cell are transmitted to a corresponding bit line BL (or/BL). At this time the amount of potential change generated on the bit line BL (or/BL) is proportional to the ratio Cs/Cb of the capacitance Cs of the memory cell capacitor to the capacitance Cb of the bit line BL (or/BL). If the bit line BL (or/BL) is made shorter, the bit line capacitance Cb can be reduced. Therefore, the amount of potential change generated on the bit line can be increased. In operation, sensing operation in the memory block (memory block DMB2 in FIG. 3) including the word line WL selected by the row decoder 502 is carried out only, and other blocks are kept in a standby state. Consequently, power consumption associated with charging/discharging of the bit lines during sensing operation can be reduced. When the above described partial activation type CDRAM is applied to the DRAM shown in FIG. 3, a SRAM register and a block decoder must be provided for each of the memory blocks DMB1 to DMB8, which significantly increases the chip area. In this structure, only SRAM cache registers corresponding to the selected block operate, and therefore, efficiency in using the SRAM cache registers is low. Further, the bit lines of the DRAM array and of the SRAM array are in one to one correspondence, as described above. When direct mapping method is employed as the method of mapping memories between the main memory and the cache memory, then the SRAM 506 is formed by 1024 cache registers arranged in one row, as shown in FIG. 2. In this case, the capacity of the SRAM cache is 1K bits. When 4 way set associative method is employed as the mapping method, the SRAM array 506 includes 4 rows of cache registers 506a to 506d as shown in FIG. 4. One of the 4 rows of cache registers 506a to 506d is selected by the selector 510 in accordance with a way address. In this case, the capacity of the SRAM cache is 4K bits. As described above, the method of memory cell mapping between the DRAM array and the cache memory is determined dependent on the internal structure on the chip. When the mapping method is to be changed, the cache size also must be changed. In both of the CDRAM structures described above, the bit lines of the DRAM array and the SRAM array are in one to one correspondence. Therefore, the column address of the DRAM array is inevitably the same as the column address of the SRAM array. Therefore, full associative method in which memory cells of the DRAM array are mapped to an arbitrary position of the SRAM array is impossible in principle. Another structure of a semiconductor memory device in which the DRAM and the SRAM are integrated on the same chip is disclosed in Japanese Patent Laying-Open No. 2-87392. In this prior art, the DRAM array and the SRAM array are connected through an internal common data bus. The internal common data bus is connected to an input/output buffer for inputting/outputting data to and from the outside of the device. Selected memory cells of the DRAM array and the SRAM array can be designated by separate addresses. However, in this structure of the prior art, data transfer between the DRAM array and the SRAM array is carried out by an internal common data bus, and therefore the number of bits which can be transferred at one time is limited by the number of internal data bus lines, which prevents high speed rewriting of the contents of the cache memory. Therefore, as in the above described structure in which the SRAM cache is provided outside the standard DRAM, the speed of data transfer between the DRAM array and the SRAM array becomes a bottleneck, preventing provision of a high speed cache memory system. (iii) Consideration on a general clock synchronized type semiconductor device for the problems of which the present invention includes the solution. A semiconductor memory device of an application specific IC (ASIC) or for pipe line usage operates in synchronization with an external clock signal such as a system clock. Operation mode of a semiconductor memory device is determined dependent on states of external control signals at rising or falling edge of the external clock signal. The external clock signal is applied to the semiconductor memory device no matter whether the semiconductor memory device is being accessed or not. In this structure, in response to the external clock signal, input buffers or the like receiving the external control signals, address signals and data operate. In view of power consumption, it is preferred not to apply the external clock signal to the semiconductor memory device when the semiconductor memory device is not accessed, or to elongate period of the external clock signal. Generally, a row address signal and the column address signal are applied multiplexed time divisionally to the DRAM. The row address signal and the column address signal are taken in the device in synchronization with the external clock signal. Therefore, when the conventional DRAM is operated in synchronization with the external clock signal, it takes long time to take the row address signal and the column address signal. Therefore, if low power consumption is given priority, the DRAM can not be operated at high speed. If the conventional semiconductor memory device is operated in synchronization with the external clock signal, the speed of operation is determined solely by the external clock signal. If the semiconductor memory device is to be used where low power consumption is given priority over the high speed operation with the speed defined by the external clock signal, the conventional clock synchronized type semiconductor memory device can not be used for such application. In a clock synchronized type semiconductor memory device, control signals and address signals are taken inside in synchronization with the clock signal. The control signals and address signals are taken inside by buffer circuits. Each buffer circuit is activated in synchronization with the clock signal and generates an internal signal corresponding to the applied external signal. In a standby state or the like, valid control signals and valid address signals are not applied. However, external clock signals are continuously applied, causing unnecessary operations of the buffer circuits. This prevents reduction in power consumption during standby state. If the cycle period of the external clock signal becomes shorter, the number of operations of the buffer circuits is increased, causing increase of power consumption during standby period. This is a serious problem in realizing low power consumption. (iv) Consideration on the problems in refreshing operation in a conventional RAM If the semiconductor memory device includes dynamic memory cells (DRAM cells), the DRAM cells must be periodically refreshed. The refresh mode of a DRAM generally includes an auto refresh mode and a self refresh mode, as shown in FIGS. 5 and 6. FIG. 5 shows waveforms in the auto refresh operation. In the auto refresh mode, a chip select signal *CE is set to "H" and an external refresh designating signal *REF is set to "L". In response to a fall of the external refresh designating signal *REF, an internal control signal int. *RAS for driving row selecting circuitry falls to "L". In response to the internal control signal int. *RAS, a Word line is selected in accordance with a refresh address generated from a built-in address counter, and memory cells connected to the selected word line are refreshed. In the auto refresh mode, the timing of refreshing the semiconductor memory device is determined by the externally applied refresh designating signal *REF. Therefore, whether or not refreshing is being carried out in the semiconductor memory device can be known outside the memory device. FIG. 6 shows waveforms in the self refresh operation. In the self refresh mode, the chip select signal *CE is set to "H" and the external refresh designating signal *REF is set to "L". When the external refresh designating signal *REF falls to "L", the external control signal int. *RAS is generated, and a word line is selected in accordance with the refresh address from the built-in address counter. Thereafter, sensing operation and rewriting of the memory cells connected to the selected word line are carried out, and the memory cells connected to the word line WL are refreshed. The first cycle of self refreshing is the same as that of auto refreshing. When the chip select signal *CE is at "H" and the refresh designating signal *REF is kept at "L" for a predetermined time period TF or longer, a refresh request signal is generated from a built-in timer. In response, the internal control signal int. *RAS is generated, the word line is selected and the memory cells connected to the selected word line are refreshed. This operation is repeated while the refresh designating signal *REF is at "L". In the refreshing operation in the self refresh mode, the timings of refreshing are determined by a timer contained in the semiconductor memory device. Therefore, timings of refreshing can not be known from the outside. Normally, data can not be externally accessed in the self refresh mode. Therefore, in the normal mode, self refreshing is not carried out. The self refresh mode is generally carried out at a standby for retaining the data. Different semiconductor chips have different upper limits of refresh period necessary for retaining data (see NIKKEI ELECTRONICS, Apr. 6, 1987, p. 170, for example). Generally, a guaranteed value for retaining data is measured by testing the semiconductor memory device, and period of a timer defining the self refresh cycle is programmed in accordance with the guaranteed value, for carrying out self refreshing. When auto refresh mode and self refresh mode are selectively used, the guaranteed value for retaining data must be measured in order to determine the self refresh cycle. As shown in FIG. 6, in the self refresh mode, an operation similar to that in the auto refreshing is carried out in response to the external refresh designating signal *REF, and then refreshing operation in accordance with the timer is carried out. Therefore, in an accurate sense, the self refresh cycle means a cycle carried out after a lapse of a prescribed time period TF successive to the auto refreshing. In the self refresh cycle, the refresh timing is determined by the contained timer, as described above, and the timings of refreshing can not be known from the outside. Therefore, the self refresh cycle can not be used as a method of hidden refreshing, for example, in a normal operation mode. (v) Consideration on Array Arrangement in CDRAM and data transfer between CDRAM and MPU (burst mode) In a semiconductor memory device containing a DRAM array and a SRAM array, it is preferred to transfer data at high speed from the DRAM array to the SRAM array, so as to enable high speed operation. When data are transferred from the DRAM array to the SRAM array, a row (word line) is selected, data of the memory cells connected to the selected word line are detected and amplified, and then a column is selected in the DRAM array. Generally, a row address signal and a column address signal are applied multiplexed to the DRAM. Therefore, increase of the speed of data transfer from the DRAM array to the SRAM array is limited by this address multiplexing. In this case, it is possible to apply the row address and the column address simply in accordance with a non-multiplex method to the DRAM. However, in that case, the number of terminals for inputting DRAM addresses are increased significantly. When the number of terminals is increased, the chip size and the package size are increased, which is not preferable. In addition, data transfer from the DRAM array to the SRAM array must be done after detection and amplification of the memory cell data by the sense amplifiers. Therefore, data transfer from the DRAM array to the SRAM array can not be carried out at high speed. Further, some external operational processing units such as a CPU (Central Processing Unit) include a data transfer mode called a burst mode for carrying out data transfer at high speed. In the burst mode, a group of data blocks are transferred successively. A block of data is stored at successively adjacent address positions. Since the burst mode is a high speed data transfer mode, the data blocks are stored in the cache memory in the semiconductor memory device containing a cache. A semiconductor memory device containing a cache which can be easily connected to an operational processing unit having burst mode function has not yet been provided. In order to implement a CDRAM, DRAM array and SRAM array are integrated on the same semiconductor chip. The semiconductor chip is housed in a package. The layout of DRAM array and SRAM array as well as the geometrical figures thereof on the chip are determined by the geometrical figure and the physical dimensions of the housing package. DRAM array and its associated circuitry occupy a major area of a chip in CDRAM because DRAM is employed as a large storage capacity memory. Thus, the size and figure of DRAM array are substantially determined by the size and shape of the housing package. In order to efficiently use the chip area, SRAM array should be arranged or laid out on the chip efficiently. However, no consideration has made on the configuration of SRAM array for implementing efficient chip area utilization and for housing CDRAM in a package of an arbitrary shape and size. SUMMARY OF THE INVENTION An object of the present invention is to provide a novel CDRAM with various operational functions and efficient chip layout. Another object of the present invention is to provide a semiconductor memory device in which self refreshing can be carried out in the normal mode. A further object of the present invention is to provide a semiconductor memory device allowing data transfer between DRAM array and a SRAM array at a high speed and with less power consumption. A further another object of the present invention is to provide a clock synchronized type semiconductor memory device in which power consumption at standby mode can be significantly reduced. A still further object of the present invention is to provide a semiconductor memory device which can be accessed at high speed even at a cache miss (miss hit). A still further object of the present invention is to provide a semiconductor memory device containing a cache which can be easily connected to an arithmetic operation unit having burst mode function. A still further object of the present invention is to provide a semiconductor memory device which operates at high speed even if the period of external clock signals is made longer. A still further object of the present invention is to provide a clock synchronized type semiconductor memory device which surely operates even if the period of the external clock signal is made longer or even if the external clock signal is generated intermittently. A still further object of the present invention is to provide a semiconductor memory device containing a cache which operates at high speed without malfunction with low power consumption. A still further object of the present invention is to provide a semiconductor memory device containing a cache which operates in synchronization with clocks, and operates at high speed without malfunction under low power consumption. A still further object of the present invention is to provide a semiconductor memory device which can be readily applied to use where high speed operation is given priority and to use where low power consumption is given priority. A still further object of the present invention is to provide a semiconductor memory device containing a cache which easily realizes high speed operation and low power consumption dependent on the intended use. A still further object of the present invention is to provide a semiconductor memory device containing a cache operating in synchronization with clocks which easily realizes both high speed operation and low power consumption dependent on intended use. A still further another object of the present invention is to provide an array arrangement which allows effective use of chip area. Yet another object of the present invention is to provide an SRAM array arrangement having a flexible array structure which can easily correspond to an arbitrary shape of the DRAM array. A yet further object of the present invention is to provide a semiconductor memory device containing a cache having an array arrangement having high density and suitable for high degree of integration. The present invention includes various aspects each of which is recited independently of others in the following. A semiconductor memory device in accordance with a first aspect of the present invention includes a DRAM array having dynamic memory cells; means for generating a refresh address; an automatic refresh means for refreshing the DRAM array in response to an external refresh designation; timer means measuring time for outputting a refresh request every prescribed timing; refresh means for refreshing the DRAM array in response to the refresh request from the timer means; refresh mode setting means for setting the refresh mode to either the auto refresh or self refresh mode; and input/output switching means for setting one pin terminal to a refresh designating input terminal or to a self refresh execution designating output terminal, in accordance with the refresh mode set by refresh mode setting means. The timer means is activated when self refresh mode is set by the refresh mode setting means. In accordance with a second aspect of the present invention, the semiconductor memory device comprises first and second memory cell arrays each including a plurality of memory cells arranged in rows and columns; a first row address input terminal for receiving a first row address for designating a row of the first memory cell array; a first column address input terminal for receiving a first column address for designating a column of the first memory cell array; a second row address input terminal for receiving a second row address for designating a row of the second memory cell array; and a second column address input terminal for receiving a second column address for designating a column of the second memory cell array. The first row address input terminal and the first column address input terminal include input terminals different from each other. The second row address input terminal and the second column address input terminal include input terminals which are different from each other. The first column address input terminal includes a pin arrangement which is shared with at least one of the second row address input terminal and the second column address input terminal. In accordance with the third aspect of the present invention, the semiconductor memory device includes first and second memory cell arrays each including a plurality of memory cells arranged in rows and columns; first address means for generating a first internal row address signal and a first internal column address signal for designating a row and a column of the first memory cell array in accordance with an external address; and second address means for generating a second internal row address and a second internal column address for designating a row and a column of the second memory cell array in accordance with the external address. The first and second address means are activated in synchronization with an external clock signal, and simultaneously generates the first internal row address signal, the first internal column address signal, the second internal row address signal and the second internal column address signal in accordance with the timing determined by the clock signal. The semiconductor memory device in accordance with the fourth aspect of the present invention includes a DRAM array including a plurality of dynamic memory cells arranged in rows and columns; an SRAM array including a plurality of static memory cells arranged in rows and columns; data transfer means provided separate from an internal data transmitting line for transferring data between the DRAM array and the SRAM array; sense amplifier means for detecting and amplifying information of the selected memory cells of the DRAM array; and control means responsive to a transfer designation from the DRAM array to the SRAM array for activating the transferring means at a timing earlier than the timing of activating the sense amplifier means. Bit line data of the DRAM array are transmitted directly to the transfer means, not through the internal data line. The semiconductor memory device in accordance with the fifth aspect of the present invention includes a DRAM array including a plurality of dynamic memory cells arranged in rows and columns; an SRAM array including a plurality of static memory cells arranged in rows and columns; amplifying means provided for each column of the DRAM array for amplifying signals on the corresponding column; sense amplifier means for amplifying and latching signals on the corresponding column; data transfer means provided separate from an internal data transmitting line for transferring data between the DRAM array and the SRAM array; means responsive to an address signal for selectively transmitting outputs from the amplifying means to the data transferring means; and control means responsive to a data transfer designation for activating the data transferring means before the activation of the sense amplifier means. The transfer mean includes means for forming a current mirror amplifying means by supplying current to the amplifying means. In accordance with a sixth aspect of the present invention, the semiconductor memory device includes address input means for receiving address signals; address generating means responsive to a burst mode designation for successively generating address signals at prescribed timings; address selecting means receiving an output from address input means and an output from address generating means, responsive to the burst mode designation for selectively passing the output of the address generating means; and memory cell selecting means for selecting a corresponding memory cell out of a plurality of memory cells in accordance with the output from the address selecting means. In accordance with a seventh aspect of the present invention, the semiconductor memory device includes address input means for receiving addresses applied from an external arithmetic processing unit; address generating means responsive to a burst mode designation from the external arithmetic processing unit for generating addresses in synchronization with external clock signals; address selecting means for selectively passing an output from address input means or an output from address generating means; and memory cell selecting means for selecting a corresponding memory cell from the memory cell array in accordance with the output from the address selecting means. The address selecting means selectively passes the output from the address generating means in response to the burst mode designation. In accordance with the eighth aspect of the present invention, the memory device includes internal clock generating means responsive to an external clock signal for generating an internal clock signal, and setting means for setting the internal clock generating means to operation inhibited state in response to a standby state designating signal. The externally applied signal is taken in response to the internal clock signal generated from the internal clock generating means. In accordance with a ninth aspect of the present invention, the semiconductor device includes, in addition to those provided in the eighth aspect, refreshing means responsive to the inhibition of the internal clock generation by the setting means for refreshing dynamic memory cells. A semiconductor memory device in accordance with a tenth aspect of the present invention includes a memory cell array having a plurality of memory cells arranged in rows and columns, and internal address generating means receiving an external address signal for generating an internal address signal. The external address signal includes an external row address signal for designating a row of the memory cell array, and an external column address signal for designating a column of the memory cell array. The internal address generating means generates internal row address signal and internal column address signal corresponding to the external row address signal and the external column address signal, respectively. The internal address generating means of the semiconductor memory device in accordance with the tenth aspect of the present invention includes first address generating means which takes one of the above mentioned external row address signal and the external column address signal at a first timing of an externally applied clock signal for generating a first internal address signal corresponding to the taken external address signal, and second address generating means which takes the other one of the external row address signal and the external column address signal at a second timing of the externally applied clock signal for generating a second internal address corresponding to the taken external address signal. The first timing is determined by one of the rise and fall of the externally applied clock signal, and the second timing is determined by the other one of the rise and fall of the externally applied clock signal. The semiconductor memory device in accordance with an eleventh aspect of the present invention includes a memory cell array including a plurality of memory cells, and address generating means receiving externally applied external address signal for generating an internal address signal corresponding to the received external address signal. The external address signal designates a memory cell in the memory cell array. The semiconductor memory device in accordance with the eleventh aspect of the present invention further includes setting means responsive to an externally applied timing designating signal for taking an address for setting the timing for the address generating means to take the externally applied address signal. The address generating means takes the applied external address signal in accordance with the timing set by the setting means and generates the internal address signal. The semiconductor memory device in accordance with the twelfth aspect of the present invention includes a DRAM array including a plurality of dynamic memory cells arranged in rows and columns, an SRAM array including a plurality of static memory cells arranged in a matrix of rows and columns, and data transferring means provided between the DRAM array and the SRAM array for transferring data between a selected memory cell of the DRAM array and a selected memory cell in the SRAM array. Each row of the matrix of the SRAM array includes memory cells divided into n groups. The SRAM array further includes a plurality of word lines each connected to memory cells of different group, n word lines being arranged for each row in parallel to the row direction of the matrix. A semiconductor memory device in accordance with a thirteenth aspect of the invention includes a high speed memory array having a plurality of static type memory cells, a large storage capacity memory array having a plurality of memory cells, and data transfer means for transferring data between a selected static type memory cell and a selected dynamic type memory cell. The semiconductor memory device of the thirteenth aspect further includes a data transfer bus for coupling the selected memory cell of the large storage capacity memory array with the data transfer means, clamping means for clamping the potential on the data transfer bus, and control means responsive to an indication of data transfer from the high speed memory array to the large storage capacity memory array for inhibiting a clamping operation of the clamping means. A semiconductor memory device in accordance with a fourteenth aspect of the invention includes a high speed memory array having a plurality of static type memory cells arranged in rows and columns, a large storage capacity memory array having a plurality of dynamic type memory cells, and data transfer means for transfer data between a selected static type and a selected dynamic type memory cell. The semiconductor memory device in accordance with the fourteenth aspect further includes clamping means provided for each column of the high speed memory array for clamping the potential of an associated column, and control means responsive to an indication of data transfer from the large storage capacity memory array to the high speed memory array for inhibiting a clamping operation by the clamping means. According to the first aspect of the present invention, setting of the self refresh mode or the auto refresh mode is done by refresh mode setting means and one terminal is switched by the input/output switching means to be a refresh designating input terminal in the auto refresh mode, and the self refresh execution designating output terminal in the self refresh mode. Therefore, even in the self refresh mode, refresh timing can be known from the outside of the memory device, and self refresh mode can be utilized even in the normal mode. In accordance with the second aspect of the present invention, since the row and column designating input terminals of the first and second memory cell array are provided separately for inputting the row address signals and the column address signals, the row address signals and the column address signals to the first and second memory cell arrays can be applied in the non-multiplexed manner. Part of the address signals to the first memory cell array and address signals to the second memory cell array is applied to the same input terminal. Therefore, address non-multiplex method can be realized without increasing the number of input terminals. According to the third aspect of the present invention, the first and second address means generate internal address signals by simultaneously taking address signals in synchronization with the external clock signal, and therefore the clock synchronized type semiconductor memory device can be operated at high speed employing address non-multiplex method. According to the fourth aspect of the present invention, data transfer means is activated at an earlier timing than the activation of the sense amplifier in the DRAM array, and therefore data can be transferred from the DRAM array to the SRAM array at high speed. According to the fifth aspect of the present invention, an output from a current mirror type amplifier is transmitted through the data transfer means, and therefore the data transfer means can be activated without waiting for the activation of the latch type sense amplifier, which enables high speed data transfer from the DRAM array to the SRAM array. According to the sixth aspect of the present invention, an internal counter is activated in response to a burst mode designation from an external arithmetic processing unit, an output from the address counter is selected by a multiplexer to be utilized as an address signal, and the multiplexer selects external address signals in a mode other than the burst mode. Therefore, a semiconductor memory device which can be easily connected to an external arithmetic processing unit having burst mode function can be provided. According to the seventh aspect of the present invention, a counter as a built-in address generator effects counting operation in synchronization with the external clock signal, the output from the counter is used as an address in the burst mode, and external address signals are taken and utilized in synchronization with an external clock signal in operation modes other than the burst mode. Therefore, a clock synchronized type semiconductor memory device which can be easily connected to an external operational processing unit having burst mode function can be realized. According to the eighth aspect of the present invention, when generation of the internal clock signal is stopped at the standby state of the clock synchronized type semiconductor memory device, operations of external signal input buffer and the like are stopped, so that power consumption in the standby state can be reduced. According to the ninth aspect of the present invention, self refresh mode is activated when generation of the internal clock signal is stopped in the invention in accordance with the eighth aspect, and therefore data of the DRAM array can be surely retained in the standby state. According to the tenth aspect of the present invention, since the external row address signals and the external column address signals are taken at timings determined by the rise and fall of the external clock signals, the external row address signal and the external column address signal can be taken by a single pulse of the external clock signal. Therefore, compared with a structure in which the external row address signal and the external column address signal are taken time divisionally at timings determined by the rise of the external clock signal, the external row address signal and the external column address signal can be taken sooner. Generally, operation of a clock synchronized type semiconductor memory device starts after the external address signals are taken. Therefore, the semiconductor memory device can be operated at higher speed. According to the eleventh aspect of the present invention, the timing for taking the external address signals is determined by timing information set by setting means. Therefore, time required for taking the external address signals can be set to an optimal value dependent on the period of the external clock signals, and therefore higher speed of operation and lower power consumption can be flexibly realized. In the SRAM array according to the twelfth aspect , memory cells arranged in one row is divided into a plurality of groups. Memory cells of each group is connected to a word line provided corresponding to each group. Therefore, memory cells of one row of the SRAM array are connected to a plurality of word lines. By adjusting the number n of the groups of the memory cells of one row, an SRAM array having an arbitrary shape can be provided without changing the number of memory cells connected to one word line. In the semiconductor memory device according to the thirteenth and fourteenth aspects, the control means is operable to inhibit the clamping operation of the clamping means provided at the data receiving side. Consequently, a current flow is prevented from flowing into the data transfer means from the clamping means, resulting in reduced current consumption. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS This application includes a large number of the drawing figures, and we first classify the figures according to the embodiments for the reader's convenience. FIGS. 1 through 6 are related to a conventional memory device. FIGS. 7 through 31 represent an array arrangement of CDRAM of the present invention. FIGS. 32 represents an overall view of a functional construction of the CDRAM. FIGS. 33 through 43B represent data outputting operation of the CDRAM. FIGS. 44 through 60D represents data transfer between DRAM array and SRAM array. FIGS. 61 through 70 represent modified data transfer arrangement with clamping circuitry. FIGS. 71 through 75 represent peripheral circuitry of the CDRAM. FIGS. 76 to 80 represent the usage of CDRAM in a system. FIGS. 81 through 104 represent specific operation modes of the CDRAM. FIG. 105 shows an overall construction of another CDRAM according to the present invention. FIGS. 106 through 118 are related to high speed and low power operation modes. FIGS. 119 through 161 represent specific operations of another CDRAM. FIGS. 162 through 175 represent selective usage of the auto-refreshing and self refreshing. FIGS. 176 through 185 represent common usage of DRAM column address and SRAM row address. FIGS. 186 through 193 represent separated I/O structure type DRAM array of another CDRAM. FIGS. 194 through 196 represent modified separated IO array architecture CDRAM for fast data transfer by means of clamping circuitry. FIGS. 197 through 201 represent burst mode operation in CDRAM's of the present invention. FIGS. 202 through 214 represent sleep mode operation in CDRAMs of the present invention. FIG. 215 summarizes the internal operations of another CDRAM. Now, respective figures are described in the following. FIG. 1 shows a structure of a memory array in a conventional dynamic semiconductor memory device. FIG. 2 shows a structure of an array portion in a conventional semiconductor memory device containing a cache. FIG. 3 shows, as an example, a layout of the cache and the DRAM array in the conventional semiconductor memory device containing a cache. FIG. 4 shows a structure of a cache when 4 way set associative method is realized by the conventional semiconductor memory device containing a cache. FIG. 5 is a diagram of signal waveforms showing the operation in the automatic refreshing in the conventional semiconductor memory device. FIG. 6 is a diagram of signal waveforms showing self refreshing operation in the conventional semiconductor memory device. FIG. 7 schematically shows a structure of a memory array portion of the semiconductor memory device according to an embodiment of the invention. FIG. 8 shows detailed structure of the memory array shown in FIG. 7. FIG. 9 shows another example of the structure of the array arrangement in the semiconductor memory device according to an embodiment of the invention. FIG. 10 shows array arrangement of a semiconductor memory device containing a 4M bit DRAM and a 16K bit SRAM. FIG. 11 shows layout of DRAM array signal lines in one memory block of the semiconductor memory device shown in FIG. 10. FIG. 12 schematically shows structures of a bit line and a word line related to a memory cell of the DRAM shown in FIG. 10. FIG. 13 schematically shows a structure of a word line in the semiconductor memory device of FIG. 10. FIG. 14 shows layout of signal lines in the semiconductor memory device shown in FIG. 10. FIG. 15 shows a structure of an SRAM array of the semiconductor memory device shown in FIG. 5. FIG. 16 shows a structure of a conventional SRAM cell. FIG. 17 is a diagram of signal waveforms showing the operation of the SRAM cell shown in FIG. 16. FIG. 18 shows an example of a shape of a package for a semiconductor memory device containing a cache, and SRAM array and DRAM array arrangements contained therein. FIG. 19 shows problems of the general SRAM array. FIG. 20 is a diagram showing problems of the general SRAM array arrangement. FIG. 21 shows a principle of the SRAM array arrangement of the present invention. FIG. 22 shows, in comparison, the arrangement of the SRAM array of the present invention and the prior art arrangement. FIG. 23 shows a pattern layout of the SRAM cell shown in FIG. 21. FIG. 24 shows an SRAM array structure of the semiconductor memory device containing a cache in accordance with one embodiment of the present invention. FIG. 25 shows an example of a transfer gate circuit structure shown in FIG. 24. FIG. 26 shows an example of a specific structure of the selecting circuit shown in FIG. 25. FIG. 27 shows a structure of the SRAM array arrangement and a structure of a transfer gate circuit employed for that SRAM arrangement. FIG. 28 shows a specific structure of a transfer path from the SRAM array to the DRAM array of the transfer gate circuit shown in FIG. 27. FIG. 29 shows a detailed structure of the data transfer path from the DRAM array to the SRAM array of the transfer gate circuit shown in FIG. 27. FIG. 30 is a diagram of signal waveforms showing the operation of the transfer gate circuit shown in FIGS. 27 to 29. FIG. 31 shows a pin arrangement and a package for containing the semiconductor memory device shown in FIG. 5. FIG. 32 shows functionally the whole structure of a semiconductor memory device containing a cache in accordance with one embodiment of the present invention. FIG. 33 shows manner of connections of the bit lines in the DRAM array and bit lines in the SRAM array with internal data line in the semiconductor memory device shown in FIG. 32. FIG. 34 shows an example of a structure of a data input/output circuit of the semiconductor memory device shown in FIG. 32. FIG. 35 shows another example of the data input/output circuit of the semiconductor memory device shown in FIG. 32. FIG. 36 shows a further example of the data input/output circuit of the semiconductor memory device shown in FIG. 32. FIG. 37 shows a circuit structure for setting data output mode of the semiconductor memory device shown in FIG. 32. FIG. 38 shows a structure of an output circuit shown in FIG. 36. FIG. 39 shows an example of a specific structure of a latch circuit shown in FIG. 37. FIG. 40 is a block diagram showing a structure of an output control circuit shown in FIG. 36. FIG. 41 shows timings of operations in latch output mode of the circuit shown in FIG. 37. FIG. 42 shows timings of operations in register output mode of the circuit shown in FIG. 37. FIG. 43 shows timing of operations in transparent output mode of the circuit shown in FIG. 37. FIG. 44 shows an example of a specific structure of a data transfer circuit in the semiconductor memory device shown in FIG. 32. FIG. 45 is a diagram of signal waveforms showing data transfer operation from the DRAM array to the SRAM array when the transfer gate circuit shown in FIG. 44 is employed. FIG. 46 is a diagram of signal waveforms showing data transfer operation from the SRAM array to the DRAM array. FIG. 47 is another diagram of signal waveforms showing data transfer operation from the DRAM array to the SRAM array when the bi-directional data transfer circuit shown in FIG. 44 is employed. FIGS. 48A through 48F show, as an example, data transfer operation at a cache miss in the semiconductor memory device shown in FIG. 32. FIG. 49 shows another example of the structure of the bi-directional transfer gate circuit. FIG. 50 shows specific structure of the circuit shown in FIG. 49. FIG. 51 shows data transfer operation from the DRAM array to the SRAM array by the circuit shown in FIGS. 49 and 50. FIGS. 52A through 52D show, as an example, data transfer operation shown in FIG. 51. FIG. 53 is a diagram of signal waveforms showing data transfer operation from the SRAM array to the DRAM array when the data transfer circuit shown in FIGS. 49 and 50 is employed. FIG. 54 shows, as an example, data transfer operation shown in FIG. 53. FIG. 55 is a diagram of signal waveforms showing data transfer operation from the DRAM array to the SRAM array at a cache miss reading, when the transfer gate circuit shown in FIGS. 49 and 50 is employed. FIGS. 56A through 56F show, as an example, data transfer operation shown in FIG. 55. FIG. 57 shows another example of the structure of the bi-directional data transfer gate. FIG. 58 shows detailed structure of the circuit shown in FIG. 57. FIG. 59 is a diagram of signal waveforms showing data transfer operation from the DRAM array to the SRAM array when the circuit of FIG. 57 is employed. FIGS. 60A through 60D show, as an example, data transfer operation shown in FIG. 59. FIG. 61 shows a modified array arrangement of CDRAM with clamping circuitry. FIG. 62 shows an equivalent arrangement to the arrangement of FIG. 61. FIG. 63 shows a specific construction of the bi-directional transfer gate of FIG. 62. FIG. 64 is a waveform diagram showing data transfer from DRAM to SRAM with the transfer gate of FIG. 63. FIG. 65 is a waveform diagram showing data transfer from SRAM to DRAM with the transfer gate of FIG. 63. FIG. 66 shows another construction of the bi-directional transfer gate of FIG. 63. FIG. 67 shows further another construction of the bi-directional transfer gate of FIG. 62. FIG. 68 is a waveform diagram showing data transfer from DRAM to SRAM with the transfer gate of FIG. 67. FIG. 69 is a waveform diagram showing data transfer from the latch circuit to DRAM with the transfer gate of FIG. 67. FIG. 70 shows another construction of the clamping circuit. FIG. 71 shows an example of the manner of allottance of DRAM addresses and SRAM addresses in the semiconductor memory device shown in FIG. 32. FIG. 72 shows another structure for allotting DRAM addresses and SRAM addresses in the semiconductor memory device shown in FIG. 32. FIG. 73 shows a manner of connection between internal data lines and SRAM bit line pairs when addresses are allotted in the manner shown in FIG. 72. FIG. 74 functionally shows the structure of the transfer gate control circuit shown in FIG. 32. FIG. 75 shows functional structure of a DRAM driving circuit shown in FIG. 32. FIG. 76 is a table showing combinations of control signals for effecting various operations realized by the semiconductor memory device shown in FIG. 10. FIG. 77 shows combinations of command registers of the semiconductor memory device shown in FIG. 32 and control signals for selecting the command registers. FIG. 78 shows, as an example, a function realized by the command register shown in FIG. 77. FIG. 79 shows one example of a manner of connection between the semiconductor memory device shown in FIG. 10 and an external CPU. FIG. 80 shows another example of the manner of connection between the semiconductor memory device containing a cache shown in FIG. 10 and an external CPU. FIG. 81 shows timings of cache hit writing operation in the semiconductor memory device shown in FIG. 10. FIG. 82 shows timings showing cache hit reading operation in transparent output mode of the semiconductor memory device shown in FIG. 10. FIG. 83 shows timings showing cache hit reading operation in latch output mode in the semiconductor memory device shown in FIG. 10. FIG. 84 shows timings of cache hit reading operation in a register output mode in the semiconductor memory device shown in FIG. 10. FIG. 85 shows timings for setting a copy back operation in the semiconductor memory device shown in FIG. 5. FIG. 86 shows timings for setting a block transfer operation in the semiconductor memory device shown in FIG. 10. FIG. 87 shows timings for setting an array writing operation in the semiconductor memory device shown in FIG. 10. FIG. 88 shows timings of control signals for setting an array reading operation in the semiconductor memory device shown in FIG. 10. FIG. 89 shows timings for setting an array active cycle in the semiconductor memory device shown in FIG. 10. FIG. 90 shows timings of control signals for setting an array active operation accompanying a transparent output mode in the semiconductor memory device shown in FIG. 10. FIG. 91 shows timings of control signals for setting an array active cycle accompanied with a latched output mode in the semiconductor memory device shown in FIG. 10. FIG. 92 shows timings of control signals for setting an array active operation accompanied with the registered output mode in the semiconductor memory device shown in FIG. 10. FIG. 93 shows timings of an array read cycle in the transparent output mode in the semiconductor memory device shown in FIG. 10. FIG. 94 shows timings of array read cycle accompanied with the latched output mode in the semiconductor memory device shown in FIG. 10. FIG. 95 shows timings of array read cycle operation in the register output mode in the semiconductor memory device shown in FIG. 10. FIG. 96 shows timings of control signals for setting the refreshing operation in the semiconductor memory device shown in FIG. 10. FIG. 97 shows timings of various control signals for simultaneously carrying out the cache hit writing operation and refreshing in the semiconductor memory device shown in FIG. 10. FIG. 98 shows timings of control signals for setting refreshing operation with cache hit reading in the transparent output mode of the semiconductor memory device shown in FIG. 10. FIG. 99 shows timings of control signals for setting refreshing operation with cache reading in the latch output mode of the semiconductor memory device shown in FIG. 10. FIG. 100 shows timings of control signals for setting refreshing accompanied with cache hit reading operation in the registered output mode of the semiconductor memory device shown in FIG. 10. FIG. 101 shows timings of control signals for setting a command register setting cycle of the semiconductor memory device according to FIG. 10. FIG. 102 illustrates state transitions showing the operation at a cache miss of the semiconductor memory device shown in FIG. 10. FIG. 103 illustrates state transitions showing the array access operation in the semiconductor memory device shown in FIG. 10. FIG. 104 shows state transitions during refreshing operation of the semiconductor memory device shown in FIG. 10. FIG. 105 functionally shows a structure of a semiconductor memory device in accordance with a second embodiment of the present invention. FIG. 106 is a diagram of waveforms showing timings for taking DRAM addresses of the semiconductor memory device shown in FIG. 105. FIG. 107 shows effects provided by an address generating circuit included in the semiconductor memory device shown in FIG. 105. FIG. 108 shows another effect of the address generating circuit shown in FIG. 105. FIG. 109 shows a specific structure of the address generating circuit shown in FIG. 105. FIG. 110 shows a specific structure of a row address strobe signal generating circuit shown in FIG. 109. FIG. 111 shows a specific structure of a column address strobe signal generating circuit shown in FIG. 109. FIG. 112 shows a specific structure of a row address latch shown in FIG. 109. FIG. 113 shows a specific structure of a column address latch shown in FIG. 109. FIG. 114 shows a structure for setting timings for taking addresses of the circuit shown in FIG. 109. FIG. 115 illustrates high speed operation of the address generating circuit shown in FIG. 109. FIG. 116 illustrates an operation at a low power consumption mode of the address generating circuit shown in FIG. 109. FIG. 117 shows another structure of the column address strobe signal generating circuit shown in FIG. 109. FIG. 118 is a diagram of signal waveforms showing the operation of the circuit shown in FIG. 117. FIG. 119 is a table showing operations realized by the semiconductor memory device shown in FIG. 105 and combinations of control signal states for realizing these operations. FIG. 120 shows manner of data transfer between the SRAM array and the DRAM array of the semiconductor memory device shown in FIG. 105. FIG. 121 is a diagram of signal waveforms showing an operation at a cache miss of the semiconductor memory device shown in FIG. 105. FIG. 122 shows timings at a cache hit reading operation of the semiconductor memory device shown FIG. 105. FIG. 123 is a diagram of waveforms showing a cache hit writing operation at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 124 is a diagram of signal waveforms showing a cache hit reading operation at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 125 is a diagram of signal waveforms showing a cache miss writing operation at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 126 is a diagram of signal waveforms showing a array writing operation at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 127 is a diagram of signal waveforms showing an array writing operation accompanied with cache hit reading at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 128 is a diagram of signal waveforms showing an array writing operation accompanied with cache hit writing at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 129 is a diagram of signal waveforms showing a direct array reading operation at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 130 is a diagram of signal waveforms showing a direct array writing operation at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 131 is a diagram of signal waveforms showing a refresh array operation at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 132 is a diagram of signal waveforms showing a refresh array operation accompanied with cache hit reading at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 134 is a diagram of signal waveforms showing a refresh array operation accompanied with cache hit writing at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 134 is a diagram of signal waveforms showing a counter check reading operation at a low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 135 is a diagram of signal waveforms showing a counter check writing operation at the low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 136 is a diagram of signal waveforms showing a command register setting operation at the low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 137 shows an example of a specific operation sequence at the low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 138 shows another example of the specific operation sequence at the low power consumption mode of the semiconductor memory device shown in FIG. 105. FIG. 139 is a diagram of signal waveforms showing a cache hit reading operation in the transparent output mode in high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 140 is a diagram of signal waveforms showing the cache hit reading operation in the latched output mode of the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 141 is a diagram of signal waveforms showing a cache hit reading operation in the registered output mode in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 142 is a diagram of signal waveforms showing the cache hit writing operation in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 143 is a diagram of signal waveforms showing the cache miss reading operation in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 144 is a diagram of signal waveforms showing the cache miss reading operation accompanied with the latched output mode in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 145 is a diagram of signal waveforms showing the cache miss reading operation in the registered output mode in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 146 is a diagram of signal waveforms showing the cache miss writing operation in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 147 is a diagram of signal waveforms showing the array writing operation in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 148 is a diagram of signal waveforms showing the array writing operation accompanied with the cache hit reading in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 149 is a diagram of signal waveforms showing the array writing operation accompanied with the cache hit reading in the latched output mode in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 150 is a diagram of signal waveforms showing the array writing operation accompanied with the cache hit reading in accordance with the registered output mode in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 151 is a diagram of signal waveforms showing the array writing operation accompanied with the cache hit writing in the high speed operation mode in the semiconductor memory device shown in FIG. 105. FIG. 152 is a diagram of signal waveforms showing a direct array reading operation in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 153 is a diagram of signal waveforms showing a direct array writing operation in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 154 is a diagram of signal waveforms showing the refresh array operation in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 155 is a diagram of signal waveforms showing the refreshing operation accompanied with cache hit reading in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 156 is a diagram of signal waveforms showing the refresh array operation accompanied with cache hit writing in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 157 is a diagram of signal waveforms showing the counter check operation in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 158 is a diagram of signal waveforms showing the counter check writing operation in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 159 is a diagram of signal waveforms showing the command register setting operation in the high speed operation mode realized by the semiconductor memory device shown in FIG. 105. FIG. 160 is a diagram of signal waveforms showing an example of an operation sequence carried out in the high speed operation mode by the semiconductor memory device shown in FIG. 105. FIG. 161 shows another example of the operation sequence realized in the high speed operation mode by the semiconductor memory device shown in FIG. 105. FIG. 162 shows a structure which can selectively effect self refreshing and auto-refreshing in the semiconductor memory device shown in FIG. 32 or FIG. 105. FIG. 163 is a block diagram showing a specific structure of the clock generator shown in FIG. 162. FIG. 164 shows an example of a specific structure of the input/output switching circuit and a command register shown in FIG. 162. FIG. 165 is a diagram of signal waveforms showing the operation of the circuit shown in FIG. 162. FIG. 166 shows another example of the structure of the circuit shown in FIG. 162. FIG. 167 illustrates battery backup mode. FIG. 168 is a block diagram showing a specific structure of a BBU control shown in FIG. 166. FIG. 169 shows a structure of the clock generator shown in FIG. 166 when the battery backup mode is employed. FIG. 170 is a diagram of signal waveforms showing the operation of the circuit shown in FIG. 169. FIG. 171 shows an example of a specific structure of a RASS generating circuit shown in FIG. 169. FIG. 172 shows a structure when the structure of FIG. 162 is applied to a general DRAM. FIG. 173 shows an example of a specific structure of the clock generator shown in FIG. 172. FIG. 174 shows another example of the structures of the input/output switching circuit and the command register shown in FIG. 162. FIG. 175 shows another example of the structures of the input/output switching circuit and the command register shown in FIG. 162. FIG. 176 shows another example of the manner of allotting addresses in the semiconductor memory device shown in FIG. 32 or FIG. 105. FIG. 177 shows connection between the address buffer circuit and the address decoder in accordance with the array allotting method shown in FIG. 176. FIG. 178 shows an example of a specific structure of a determining circuit shown in FIG. 177. FIG. 179 shows, as an example, positions of dividing address signal lines in accordance with the address allotting method shown in FIG. 176. FIG. 180 shows another example of the structure for realizing the address allotting method shown in FIG. 176. FIG. 181 is a diagram of signal waveforms showing the operation of the semiconductor memory device in accordance with the address allotting method shown in FIG. 176. FIG. 182 shows timings of operations of the semiconductor memory device in accordance with the address allottance shown in FIG. 176. FIG. 183 shows, as an example, an operation of the semiconductor memory device in accordance with the address allotting method shown in FIG. 176. FIG. 184 shows, as an example, the manner of connection between an external CPU and the semiconductor memory device shown in FIG. 176. FIG. 185 shows, as an example, the manner of connection between an external CPU and the semiconductor memory device in accordance with the address allotting method shown in FIG. 176. FIG. 186 shows another example of the structure of the DRAM array. FIG. 187 is a diagram of signal waveforms showing data transfer operation from the DRAM array to the SRAM array in the memory array and transfer gate structure shown in FIG. 186. FIG. 188 is a diagram of signal waveforms showing data transfer operation from the SRAM array to the DRAM array in the structure shown in FIG. 186. FIG. 189 shows data transferring portion from the DRAM array to the SRAM array of the transfer gate shown in FIG. 186. FIG. 190 shows a circuit structure for transferring data from the SRAM array to the DRAM array of the transfer gate shown in FIG. 186. FIG. 191 shows a circuit structure for generating a signal for driving a column selecting line in FIG. 186. FIG. 192 shows a circuit structure for generating a block selecting signal shown in FIG. 186. FIG. 193 shows, as an example, an array allotting method for effectively driving the array structure shown in FIG. 186. FIG. 194 shows a modified separated IO DRAM array arrangement of CDRAM with clamping circuitry. FIG. 195 is a waveform diagram showing data transfer from DRAM to SRAM in CDRAM of FIG. 194. FIG. 196 is a waveform diagram showing data transfer from SRAM (or the latch) to DRAM in CDRAM of FIG. 194. FIG. 197 shows a circuit structure for realizing data transfer in the burst mode. FIG. 198 is a diagram of signal waveforms showing the operation of the circuit shown in FIG. 197. FIG. 199 shows an example of a specific structure of the address counter shown in FIG. 197. FIG. 200 shows an example of a specific structure of a burst data number storing circuit shown in FIG. 197. FIG. 201 shows a structure for driving a common semiconductor memory device in the burst mode. FIG. 202 shows a specific structure of the address buffer of the semiconductor memory device shown in FIG. 32 or FIG. 105. FIG. 203 shows an example of a specific structure of the control clock buffer shown in FIG. 32 or FIG. 105. FIG. 204 is a diagram of signal waveforms showing an operation in a sleep mode. FIG. 205 is a block diagram showing a circuit structure for realizing the sleep mode. FIG. 206 shows an example of a specific structure of the internal clock generating circuit shown in FIG. 205. FIG. 207 shows an example of a specific structure of the sleep control circuit shown in FIG. 205. FIG. 208 is a diagram of signal waveforms showing the operation of the circuit shown in FIG. 207. FIG. 209 shows a circuit structure for realizing self refreshing in the sleep mode. FIG. 210 shows a structure of portions related to a refresh requesting signal of the clock generator shown in FIG. 209. FIG. 211 is a diagram of signal waveforms showing the operation of the circuit shown in FIG. 209. FIG. 212 shows another example of a structure of the sleep control circuit shown in FIG. 205. FIG. 213 is a diagram of signal waveforms showing the operation of the circuit shown in FIG. 212. FIG. 214 shows, as an example, required conditions of the control signals E# and CI# for surely setting the sleep mode. FIG. 215 is a table showing operations realized by the semiconductor memory device shown in FIG. 105 in combination with the states of control signals . DESCRIPTION OF THE PREFERRED EMBODIMENTS Array arrangement of DRAM and SRAM arrays in CDRAM are described with reference to FIGS. 7 through 23. In the arrangement, DRAM array includes a plurality of blocks to implement partial activation type operation. DRAM array includes local IO lines provided for respective blocks, and global IO lines each provided for blocks arranged in a row direction. SRAM array includes a plurality of SRAM cells arranged in a matrix. Data transfer of a plurality of bits between DRAM array and SRAM array is made through bi-directional transfer gate circuit and global IO lines. DRAM address and SRAM address can be set independently of each other. This arrangement allows first data transfer in any mapping scheme between DRAM array and SRAM array, as the blocks arranged in a column direction are simultaneously activated to communicate data with corresponding global IO lines through local IO lines. Now, detailed explanation will be made on specific DRAM and SRAM array arrangements. Array Arrangement 1 FIG. 7 schematically shows a structure of a memory array portion of the semiconductor memory device in accordance with one embodiment of the present invention. Referring to FIG. 7, the semiconductor memory device comprises a DRAM array 1 including dynamic memory cells arranged in a matrix of rows and columns, a SRAM array 2 including static memory cells arranged in a matrix of rows and columns, and a bi-directional transfer gate circuit 3 for transferring data between DRAM array 1 and SRAM array 2. DRAM array 1 includes, assuming that it has storage capacity of 1M bit, 1024 word lines WL and 1024 pairs of bit lines BL and/BL. In FIG. 7, the DRAM bit line pair is denoted by DBL. DRAM array 1 is divided into a plurality of blocks along the row and column directions. In FIG. 7, DRAM array 1 is divided into 8 blocks MBi1 to MBi8 (i=1 to 4) along the column direction and divided into 4 blocks MB1j to MB4j (j=1 to 8) along the row direction, namely, it is divided into a total of 32 memory blocks as an example. 8 blocks Mbi1 to Mbi8 divided in the column direction constitute a row block 11. 4 blocks MB1j MB4j divided in the row direction constitute a column block 12. The memory blocks Mbi1 to Mbi8 included in one row block 11 share the same word line WL. The memory blocks MB1j to MB4j included in the same column block 12 shares a column selecting line CSL. A sense amplifier +IO block 13 is provided for each of the memory blocks MB11 to MB18. The structure of sense amplifier +IO block 13 will be described later. Column selecting line CSL simultaneously selects two columns (two pairs of bit lines). The semiconductor memory device further comprises a row decoder 14 responsive to an address for selecting a corresponding one row from DRAM array 1, and a column decoder 15 responsive to an applied column address for selecting one column selecting line CSL. Column blocks 12 are connected to the bi-directional transfer gate circuit 13 through two pairs of I/O lines 16a and 16b which are independent and separate from each other. SRAM array 2 includes 16 pairs of bit lines SBL which are connected to 16 pairs of I/O lines through the bi-directional transfer gates circuit 3, respectively. If SRAM array 2 has the capacity of 4K bit, it includes 16 pairs of bit lines and 256 word lines. Namely, in SRAM array 2, one row is comprised of 16 bits. SRAM array 2 is associated with a SRAM row decoder 21 for decoding a row address applied to the SRAM for selecting one row of SRAM array 2, a SRAM column decoder 22 for decoding an applied column address and for selecting a corresponding column in SRAM array 2, and a sense amplifier circuit 23 for amplifying and outputting data of the memory cell selected by SRAM row decoder 21 and SRAM column decoder 22 in data reading. The SRAM bit line pair SBL selected by SRAM column decoder 22 is connected to a common data bus, and input/output of data with the outside of the device is effected through an input/output buffer (not shown). Addresses applied to DRAM row decoder 14 and DRAM column decoder 15 are independent of addresses applied to SRAM row decoder 21 and SRAM column decoder 22, and are applied to mutually different address pin terminals from those for SRAM addresses. Data transfer operation of the semiconductor memory device shown in FIG. 7 will be briefly described. The operation of the DRAM portion will be described. First, in accordance with an externally applied row address, row decoder 14 carries out a row selecting operation and raises potential of one word line DWL to "H". Data are read to corresponding 1024 bit lines BL (or/BL) from memory cells connected to the selected one word line DWL. Then, sense amplifiers (included in the block 13) of row block 11 including the selected word line DWL are activated at one time, and differentially amplify potential difference between each bit line pair. Only one of the four row blocks 11 is activated to reduce power consumption associated with charging/discharging of the bit lines during the sensing operation. (This operation, in which only the row block including the selected row is activated, is called partial activation method.) In accordance with an externally applied column address, DRAM column decoder 15 carries out a column selecting operation and one column selecting line CSL is set to the selected state in each column block 12. The column selecting line CSL selects two pairs of bit lines, and the two pairs of bit lines are connected to two pairs of I/O lines 16a and 16b provided corresponding to the block. Consequently, a plurality of bits (16 bits in this embodiment) of data are read to the plurality of I/O line pairs 16a and 16b from DRAM array 1. Operation of the SRAM portion will be described. In accordance with an externally applied row address, SRAM row decoder 21 carries out row selecting operation and selects one word line from SRAM array 2. As described above, 16 bits of memory cells are connected to one SRAM word line. Therefore, by the selection of one word line, 16 static memory cells (SRAM cells) are connected to 16 pairs of bit lines SBL. After 16 bit data have been transmitted to I/O line pairs 16a and 16b for DRAM array 1, bi-directional transfer gate circuit 3 is turned ON, and 16 pairs of I/O lines 16a and 16b are connected to 16 pairs of bit lines SBL of the SRAM. Consequently, data which have been transmitted to 16 pairs of I/O lines 16a and 16b are written to the 16 bits of memory cells which have been selected in SRAM array 2. A sense amplifier circuit 23 and column decoder 22 provided in the SRAM are used to transfer data between the memory cells in SRAM array 2 and an input/output buffer for inputting/outputting external data. It is possible to set addresses for selecting SRAM cells in SRAM array 2 completely independent from addresses for selecting dynamic memory cells (DRAM cells) in DRAM array 1. Therefore, it is possible for the 16 bits of memory cells selected in DRAM array 1 to exchange data with memory cells at an arbitrary position (row) of SRAM array 2. Therefore, all of the direct mapping method, set associative method and full associative method can be realized without changing the structure, or the array arrangement. The principle of simultaneous transfer of 16 bits of data from the DRAM to the SRAM has been described. Simultaneous transfer of 16 bits of data from SRAM array 2 to DRAM array 1 is carried out in the same manner, except that the direction of data flow through the bi-directional transfer gate circuit 3 is reversed. The structure and operation of the semiconductor memory device containing a cache in accordance with the present invention will be described in detail. FIG. 8 shows a specific structure of a main portion of the semiconductor memory device shown in FIG. 7. FIG. 8 shows, as a representative, a portion related to data transfer of one memory block MBij of DRAM array. Referring to FIG. 8, DRAM memory block MBij includes a plurality of DRAM cells DMCs arranged in rows and columns. DRAM cell DMC includes one transistor Q0 and one capacitor C0. A constant potential Vgg is applied to one electrode (cell plate) of memory capacitor C0. The memory block MBij further includes DRAM word lines DWL to each of which one row of DRAM cells DMCs are connected, and DRAM bit line pairs DBL to each of which a column of DRAM cells DMCs are connected. The DRAM bit line pair DBL includes two bit lines BL and/BL. Signals complementary to each other are transmitted to bit lines BL and/BL. A DRAM cell DMC is arranged at a crossing of a DRAM word line DWL and a DRAM bit line pair DBL. A DRAM sense amplifier DSA for detecting and amplifying potential difference on a corresponding bit line pair is provided for each of the DRAM bit line pairs DBL. Operation of DRAM sense amplifier DSA is controlled by a sense amplifier activating circuit SAK which generates sense amplifier driving signals .phi.SAN and/.phi.SAP in response to sense amplifier activating signals .phi.SANE and/.phi.SAPE. DRAM sense amplifier DSA includes a first sense amplifier portion having p channel MOS transistors cross coupled for raising a bit line potential which is higher in a bit line pair to operational supply potential Vcc level in response to the signal /.phi.SAP, and a second sense amplifier portion having n channel MOS transistors cross coupled for discharging potential of a bit line in the pair which is at lower potential to, for example, the potential Vss of the ground potential level, in response to the signal .phi.SAN. The sense amplifier activating circuit SAK includes a sense amplifier activating transistor TR1 which is turned on in response to sense amplifier activating signal/.phi.SAPE for activating the first sense amplifier portion of DRAM sense amplifier DSA, and a sense amplifier activating transistor TR2 which is turned on in response to sense amplifier activating signal .phi.SANE for activating the second sense amplifier portion of DRAM sense amplifier DSA. Transistor TR1 is formed by a P channel MOS transistor, while the transistor TR2 is formed by an n channel MOS transistor. When turned on, transistor TR1 transmits a driving signal/.phi.SAP of the operational supply potential Vcc level to one supply node of each sense amplifier DSA. When turned on, transistor TR2 transmits a signal .phi.SAN of the potential Vss level to the other supply node of DRAM sense amplifier DSA. Between a signal line/.phi.SAP and the signal line .phi.SAN to which signals/.phi.SAP and .phi.SAN are output from sense amplifier activating circuit SAK, an equalize transistor TEQ is provided for equalizing both signal lines in response to an equalize designating signal .phi.EQ. Therefore, in the standby state, sense amplifier driving signal lines/.phi.SAP and .phi.SAN are precharged to an intermediate potential of (Vcc+Vss)/2. Signal lines and signals transmitted thereto are represented by the same reference characters. For each of the DRAM bit line pairs DBL, a precharge/equalize circuit PE which is activated in response to a precharge equalize signal .phi.EQ for precharging and equalizing bit lines of the corresponding bit line pair to a predetermined precharge potential Vb1 is provided. DRAM memory block MBij further comprises a column selecting gate CSG provided for each of the DRAM bit line pairs DBL and turned on in response to a signal potential on column selecting line CSL for connecting the corresponding DRAM bit line pair DBL to a local I/O line pair LIO. A column selecting line CSL is commonly provided for two pairs of DRAM bit lines, and therefore, two DRAM bit line pairs DBL are selected simultaneously. In order to receive data from the simultaneously selected two pairs of DRAM bit lines, two pairs of local I/O lines, that is, LIOa and LIOb are provided. Memory block MBij further comprises IO gates IOGa and IOGb responsive to a block activating signal .phi.BA for connecting the local I/O line pairs LIOa and LIOb to global I/O line pairs GIOa and GIOb, respectively. Column selecting line CSL extends in the row direction over one column block shown in FIG. 7, and global I/O line pair GIOa and GIOb also extend in the row direction over one column block. Local I/O line pair LIOa and LIOb extend only in the column direction in one memory block. I/O lines 16a and 16b in FIG. 7 correspond to local I/O line pair LIOa and LIOb, IO gates IOGa and IOGb, and global I/O line pairs GIOa and GIOb, respectively. SRAM comprises SRAM word lines SWL to each of which one row of SRAM cells SMCs are connected, SRAM bit line pairs SBL to each of which a column of SRAM cells SMCs are connected, and SRAM sense amplifiers SSA provided corresponding to the SRAM bit line pairs SBL for detecting and amplifying potential difference between the corresponding bit line pair. Bi-directional transfer gate circuit 3 comprises bi-directional transfer gates BTGa and BTGb provided between SRAM bit line pair SBL and global I/O line pair GIO. Both of bi-directional transfer gates BTGa and BTGb transfer data between SRAM bit line pair SBL and global I/O line pairs GIOa and GIOb in response to data transfer designating signals .phi.TSD and .phi.TDS. Data transfer designating signal .phi.TSD designates data transfer from SRAM portion to DRAM portion, while data transfer designating signal .phi.TDS designates data transfer from DRAM portion to SRAM portion. Array Arrangement 2 FIG. 9 shows another example of the structure of the array arrangement. In the array arrangement of FIG. 9, an SRAM column decoder 22 is provided between DRAM array 1 and SRAM array 2. An input/output buffer 274 is connected to a column selected by SRAM column decoder 22 through an internal data line 251. In the structure shown in FIG. 9, the column selected by DRAM array 1 is connected to internal data line 251 through the bi-directional transfer gate. The connection between DRAM array 1 and internal data line 251 through bi-directional transfer gate circuit 3 may be effected by the column selecting gate provided in the bi-directional transfer gate by a column selecting signal from column decoder 15 of the DRAM. The connection between DRAM array 1 and internal data line 251 and connection between SRAM array 2 and internal data line 251 will be described in detail later. An address buffer 252 takes an address signal Aa applied externally in response to a chip enable signal E and generates an internal row.column address signal int-Aa for designating a row.column of DRAM array 1. Address buffer 252 takes an externally applied address signal Ac in response to chip enable signal E and generates an internal row.column address signal int-Ac for designating a row and a column of SRAM array 2. External address signal Aa for DRAM array and address signal Ac for SRAM array are applied to address buffer 252 through separate terminals. In this structure shown in FIG. 9, internal address int-Ac applied to the row decoder 21 and column decoder 22 of SRAM and internal address int-Aa applied to row decoder 14 and column decoder 15 of DRAM are applied through independent paths. Therefore, by this structure, addresses of memory cells in SRAM array 2 and DRAM array 1 can be independently designated. In the structure shown in FIG. 9, a SRAM column decoder 22 is provided between bi-directional transfer gate circuit 3 and SRAM array 2. SRAM column decoder 22 may be provided between bi-directional transfer gate circuit 3 and DRAM array 1. Alternatively, a corresponding I/O line pair of DRAM array may be selected from I/O line pairs 16a, 16b of DRAM array 1 by an output from DRAM column decoder 15 to connect the same to internal common data bus 251, and SRAM bit line pair SBL may be connected to internal data transmitting line 251 by SRAM column decoder 22. Array Arrangement 3 FIG. 10 shows a layout of an array in a semiconductor memory device in accordance with another embodiment of the present invention. A CDRAM shown in FIG. 10 includes a 4M bit DRAM array and a 16K bit SRAM array. More specifically, the CDRAM of FIG. 10 includes 4 CDRAMs shown in FIG. 7 or 9. Referring to FIG. 10, the CDRAM includes four memory mats MM1, MM2, MM3 and MM4 each having the storage capacity of 1M bit. Each of the DRAM memory mats MM1 to MM4 includes a memory cell arrangement of 1024 rows (word lines) by 512 columns (bit line pairs). Each of the DRAM memory mats MM1 to MM4 is divided into 32 memory blocks MBs each having a structure of 128 columns (bit line pairs).times.256 rows (word lines). One memory mat MM is divided into 4 memory blocks in the row direction, and into 8 blocks in the column direction. As shown in FIG. 10, a 1M bit memory mat is divided into 8 blocks in the column direction and 4 blocks in the row direction, different from the arrangement of the DRAM of FIG. 7, in order to house the device in a rectangular package, as will be described later. Sense amplifiers DSA for DRAMs and column selecting gates CSG are arranged corresponding to respective bit line pairs DBL at the central portion in the column direction of the respective memory blocks MB. A memory block MB is divided into an upper memory block UMB and a lower memory block LMB with the sense amplifier DSA and column selecting gate CSG positioned at the center. In operation, either the upper memory block UMB or the lower memory block LMB is connected to the sense amplifier DSA and to the column selecting gate CSG. Whether the upper memory block UMB or lower memory block LMB is to be connected to sense amplifier DSA and column selecting gate CSG is determined by an address. Such a structure in which one memory block MB is divided into upper and lower two memory blocks UMB and LMB and one of the two blocks is connected to sense amplifier DSA and to column selecting gate CSG is commonly used in DRAMs having shared sense amplifier structure having the storage capacity equal to or larger than 4M bit. One memory mat MM includes two activation sections AS. One word line is selected in one activation section. Different from the structure shown in FIG. 7, one word line is divided into two portions and allotted to respective activation sections in the structure of FIG. 10. Namely, selection of one word line in one memory mat MM is equivalent to selection of one word line in each activation section AS. The semiconductor device (CDRAM) further comprises 4 DRAM row decoders DRD1, DRD2, DRD3 and DRD4 for selecting one word line from each of four DRAM memory mats MM1 to MM4. Therefore, in the CDRAM shown in FIG. 10, 4 word lines are selected at one time. DRAM row decoder DRD1 selects one row from corresponding activation sections AS of the memory mats MM1 and MM2. DRAM row decoder DRD2 selects one row from lower activation sections AS of memory mats MM1 and MM2. DRAM row decoders DRD3 and DRD4 select one row from upper activation sections AS of DRAM memory mats MM3 and MM4 and from lower activation sections AS of this memory mat, respectively. The CDRAM further comprises DRAM column decoders DCD for selecting two columns (bit line pairs) from each of the column blocks of memory mats MM1 to MM4 of the DRAM. Column selection signal from the DARM column decoder DCD is transmitted to a column selection line CSL shown in FIG. 8. A column selection line CSL extends to be shared by the upper and lower activation sections AS. Therefore, in the structure shown in FIG. 10, 4 columns are selected from one column block (in FIG. 10, a block including 8 memory blocks MBs divided in the column direction), by the column selection signal from DRAM column decoder DCD. Columns selected by column decoder DCD are connected to corresponding global I/O line pairs GIO. Two pairs of global I/O lines GIO extend in the column direction in each column block in one activation section. Connection between the global I/O line pair GIO and local I/O line pair LIO in each column block will be described in detail later. CDRAM shown in FIG. 10 further includes SRAM array blocks SMA1 to SMA4 each formed of SRAM cells having the capacity of 4K bit. Row decoders SRD1 and SRD2 for SRAM are provided at a middle portion between 2 SRAM array blocks to be shared by two SRAM array blocks. SRAM row decoder SRD1 is commonly used by SRAM array blocks SMA1 and SMA3. SRAM row decoder SRD2 is commonly used by SRAM array blocks SMA2 and SMA4. Details of the structure of SRAM array block SMA will be described in detail later. The CDRAM includes 4 input/output buffer circuits IOB1, IOB2, IOB3 and IOB4 for carrying out input/output of data 4 bits by 4 bits. Input/output buffer circuits IOB1 to IOB4 are connected to blocks SCDA of sense amplifiers and column decoders for SRAM, through common data buses (internal data buses), respectively. In the structure shown in FIG. 10, input/output of data are shown to be carried out through the sense amplifier and column decoder block SCDA for the SRAM. However, input/output of data may be carried out through the portion of bi-directional transfer gates BTG. In operation, one word line is selected in each activation section AS. Only the row block including the selected word line is activated. Other row blocks are maintained at the precharge state. In the selected row block, only a small block UMB (or LMB) including the selected word line is connected to the sense amplifier DSA and column selecting gate CSG for DRAM, and the other small memory block LMB (or UMB) in the selected block is separated from sense amplifier DSA and column selecting gate CSG for DRAM. Therefore, as a whole, activation (charge/discharge) of 1/8 of bit lines is effected. By this partial activation, power consumption in charging/discharging of the bit lines can be reduced. In addition, by dividing one memory block MB into an upper memory block UMB and a lower memory block LMB and by arranging a sense amplifier DSA at the center therebetween, the bit line can be made shorter, the ratio Cb/Cs of bit line capacitance Cb to memory capacitor capacitance Cs can be reduced, and sufficient reading voltage can be obtained at high speed. In each activation section AS, sensing operation in 4 small blocks UMB (or LMB) in the row direction is carried out. In each activation section AS, two pairs of bit lines are selected in one column block by a column selection signal from DRAM column decoder DCD. Global I/O line pair GIO extends in the column direction to be shared by column blocks in each activation section AS. Two pairs of bit lines are selected from each column block in each activation section AS and connected to corresponding two pairs of global I/O lines GIO. 4 pairs of global I/O lines GIO are connected to one bi-directional transfer gate BTG. 4 bi-directional transfer gates BTG are provided for one memory mat MM. Therefore, 16 pairs of global I/O lines GIO can be connected to SRAM bit line pairs SBL of the corresponding SRAM array from one memory mat MM. Layout of the global I/O lines will be described. FIG. 11 shows arrangement of global I/O lines for one memory mat. Referring to FIG. 11, the global I/O line pair GIO includes an upper global I/O line pair UGIO provided for an upper activation section UAS and a lower global I/O line pair LGIO provided for a lower activation section LAS. The upper global I/O line pair UGIO and the lower global I/O line pair LGIO are arranged in parallel. Lower global I/O line pair GIO passes through upper activation section UAS but is not connected to local I/O line pair LIO in the upper activation section UAS. Global I/O line pair GIO and local I/O line pair LIO are connected through an IO gate IOG which is a block selecting switch. Only an IO gate IOG provided in the row block including the selected word line is turned on by a block selecting signal .phi.BA and connects the corresponding local I/O line pair LIO to the corresponding global I/O line pair GIO. Since DRAM sense amplifier DSA and column selecting gate CSG are arranged at the central portion in the column direction of the memory block MB, local I/O line pair LIO is arranged along the row direction at the central portion in the column direction of memory block MB. A word line shunt region WSR is provided in the column direction between adjacent column blocks. A word line shunt region WSR is used to provide a contact between a word line formed of polysilicon having relatively high resistance and an aluminum interconnection having low resistance. The word line shunt region will be described briefly. FIG. 12 schematically shows a cross sectional structure of a selecting transistor Q0 (see FIG. 11) included in a DRAM cell. Referring to FIG. 12, the selecting transistor Q0 includes impurity regions IPR formed at a surface of a semiconductor substrate SUB, a bit line BL connected to one impurity region IPR, and a polysilicon layer PL formed on the surface of the semiconductor substrate between the two impurity regions IPR. When a word line driving signal DWL (the signal line and the signal transmitted thereon are represented by the same reference character) is transmitted to the polysilicon layer PL, a channel is formed at the surface of the semiconductor substrate between the impurity regions IPR, and the selecting transistor Q0 is turned on. Polysilicon has relatively high resistance. If word line DWL has high resistance, a signal delay is generated due to the resistance of polysilicon. In order to lower the resistance of the word line DWL, an aluminum interconnection AL having low resistance is provided in parallel to the polysilicon layer PL. By periodically connecting the aluminum interconnection AL and the polysilicon lay |