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Home | Alpha Telephone | Domain Names | Web Hosting | Get Traffic | xrEvidence | xrSoccer United States Patent
Packet address look-ahead technique for use in implementing a high speed packet switch Apparatus, and accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch (200), particularly suited for asynchronous mode transfer (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points (550), staggered time phased contention resolution and shared memory based input and output modules (260 and 270, respectively). Each incoming packet cell has added thereto an additional header field containing information identifying a particular output module and a particular output port of that module. An input module associated with the switching crosspoints changes the additional header information to identify the particular output module of the next subsequent packet cell.
Primary Examiner: Olms; Douglas W. Assistant Examiner: Samuel; T. Attorney, Agent or Firm: Suchyta; Leonard Charles, Falk; James W. We claim: 1. In apparatus for a packet switching system having "k" substantially identical input modules each providing "n" separate incoming lines and each having "m" separate outputs and "k" substantially identical output modules each having "m" separate inputs and providing "n" separate outgoing lines, said system also having "m" substantially identical k-by-k cross-point switching planes each having a plurality of switching elements and being connected to a corresponding one of the outputs of each of the input modules and to a corresponding one of the inputs to each of said output modules, wherein the corresponding output from every one of the input modules has the same numerical ranking and the corresponding input to every one of the output modules has the same numerical ranking ("k", "m", and "n" being pre-defined integer values), the method comprising the steps of: appending a routing header to each input packet appearing over each of a plurality of input packet lines so as to form a corresponding incoming packet; delivering said corresponding incoming packet to one of "m" outputs of one of said "k" input modules, wherein said routing header in said corresponding incoming packet appearing on said one output contains a routing address for a subsequent incoming packet that is to appear on said one output, said routing address having first and second routing address fields respectively containing an address of one of the "k" output modules and an address of one of the "n" outgoing lines provided by said one output module; establishing, in response to said routing addresses contained in a first group of said incoming packets appearing on the corresponding output from all of said input modules, the configuration of said each cross-point switching plane prior to arrival on said corresponding output of all of said input modules of a second group of said incoming packets having input packets that are to be routed through said each cross-point plane in accordance with said routing addresses in said first group of incoming packets; and setting, in response to said establishing step, the states of said switching elements as defined by said configuration prior to routing said second group of incoming packets through said each cross-point plane. 2. The method in claim 1 wherein, in any one of said groups of incoming packets, each incoming packet in said one group appears on the corresponding one output from a different one of said input modules and all of said incoming packets in said one group respectively occur substantially simultaneously on the corresponding output of all of said input modules. 3. The method in claim 2 wherein said first group of incoming packets occurs one packet in advance of said second group of incoming packets. 4. The method in claim 3 wherein said each input packet is an incoming asynchronous transfer mode (ATM) cell. 5. The method in claim 4 wherein said appending step comprises the step of translating a value of a virtual channel identifier (VCI) field in said each input packet to form said routing address in said corresponding incoming packet. 6. The method in claim 5 wherein said translating step further comprises the steps of: first translating the VCI field value in said each input packet into first and second physical routing addresses; adding said first and second physical routing addresses to a front of said each input packet so as to form a corresponding first packet; and transferring, in response to a stream of said first packets having corresponding input packets that are to be routed through a common incoming line to said switching circuitry, a value of the first physical routing address from each one of said first packets as the value of the first physical routing address to a successive corresponding one of said first packets so as to form corresponding ones of said incoming packets for application over said common incoming line to said switching circuitry. 7. The method in claim 6 wherein said first translating step comprises the steps of: second translating the VCI field value into a first logical routing address; and third translating the first logical routing address into the first physical routing address. 8. Apparatus for a packet switching system comprising a plurality of incoming lines for receiving incoming packet cells, each of said incoming packet cells including data and header information, a plurality of outgoing lines for providing outgoing packets, a plurality of switching elements for routing incoming packets to said outgoing lines, means responsive to said header information of each incoming packet cell for inserting, before each said packet cell, additional internal header routing information identifying a particular switching element for that packet cell, means responsive to said additional internal header routing information for replacing a portion of said additional header routing information with a routing identification for the next subsequent incoming packet cell, and means for establishing the configuration of said switching element for each incoming packet as determined by the additional internal routing information for that packet cell and the routing identification determined by said means responsive to said additional internal routing information for the immediately prior incoming packet cell. 9. Apparatus in accordance with claim 8 wherein the header information of each incoming packet cell includes a virtual channel identification and said means for inserting information before said cell include means for translating said virtual channel information field into a subsequent virtual channel information field. 10. Apparatus in accordance with claim 8 wherein said switching elements comprise individual cross-point elements and said cross-point elements are arranged in cross-point switching planes. 11. Apparatus for a packet switching system comprising a plurality of incoming lines for receiving incoming packet cells, each of said incoming packet cells including data and header information, a plurality of outgoing lines for providing outgoing packets, a plurality of switching elements for routing incoming packets to said outgoing lines, input modules means connected to the inputs of said switching elements and output module means connected to the outputs of said switching elements, each of said output module means having a plurality of output ports, interface module means responsive to said header information of each incoming packet cell for inserting before each said packet cell additional internal header routing information identifying a specific output module means for that packet cell and a specific output port on said output module means for the packet cell, means responsive to said additional header routing information for replacing said information identifying said specific output module means for that packet cell with information identifying the specific output module means for the next packet cell, and means for establishing the configuration of said switching elements for each incoming packet as determined by the additional internal header routing information identifying said specific output module means from the immediately previous packet cell and said specific output port of said output port means from that packet cell. 12. The method of routing incoming packet cells appearing on incoming lines through switching means to outgoing lines, each of said incoming packet cells including data and header information, comprising the steps of responsive to the incoming packet cell header information inserting before each packet cell additional internal header routing information, responsive to the inserted internal header routing information determining for each packet cell replacement information with respect to operation of the switching means for the next subsequent packet cell, and operating the switching means for each packet cell responsive to both the inserted internal header routing information for that packet cell and the replacement information from the immediately prior packet cell. 13. The method in accordance with claim 12 further comprising the step of replacing a portion of the header information with information related to a subsequent switching means while inserting said additional internal header routing information before each packet cell. 14. The method in accordance with claim 12 wherein each incoming packet cell is an incoming asynchronous transfer mode packet cell. CROSS REFERENCE TO RELATED APPLICATIONS This application describes and claims subject matter that is also described in the following two co-pending United States patent applications also assigned to the present assignee hereof and filed simultaneously herewith: "A LARGE FAULT TOLERANT PACKET SWITCH PARTICULARLY SUITED FOR ASYNCHRONOUS TRANSFER MODE (ATM) COMMUNICATION", Ser. No. 629,584, now U.S. Pat. No. 5,130,984; issued Jul. 14, 1992; and "A TECHNIQUE FOR RESOLVING OUTPUT PORT CONTENTION IN A HIGH SPEED PACKET SWITCH", Ser. No. 629,576. BACKGROUND OF THE DISCLOSURE 1. Field of the Invention The invention relates to apparatus, as well as to accompanying methods for use therein, for a large (e.g. approximately 1 Terabit/second), fault tolerant packet switch, particularly suited for asynchronous transfer mode (ATM) communication, which utilizes cell address look-ahead in conjunction with parallel planes of self-routing cross-points, staggered time phased contention resolution and shared memory based input and output modules. 2. Description of the Prior Art Presently, the growing deployment of the public integrated services digital network (ISDN) throughout the nationwide telephone system permits each ISDN subscriber to gain access to a communication channel that possesses a significantly increased bandwidth over that available through a conventional telephone (i.e. POTS--plain old telephone services) connection. Although the bandwidth provided by basic rate ISDN service has the potential to provide a wide variety of new communication services to each of its subscribers, in the coming years various communication technologies that are just now emerging, such as broadband video and very high speed data transmission, are expected to impose bandwidth requirements on subscriber ISDN channels that will far exceed the bandwidth obtainable at a basic rate ISDN interface. Such an interface consists of two 64 kbit/second "B" channels and one 16 kbit/second "D" channel, where the "D" channel is a packet channel which carries signalling information for communication occurring over each B channel. For example, broadband video service offerings might include: desktop teleconferencing having voice/video/data communication from a single terminal located at one's desk, distribution video, video-on-demand, videotelephone, still video picture services and high definition television. In terms of bandwidth, just one high definition television signal is expected to require, depending upon the manner in which it is encoded, at least 45 Mbit/second of channel bandwidth. Clearly, the bandwidth of such a signal far exceeds that furnished by a basic rate ISDN channel. In an effort to provide sufficient channel bandwidth to meet expected subscriber demand in a public ISDN environment, the art has turned to implementing so-called broadband ISDN (B-ISDN). In B-ISDN, each subscriber channel is presently envisioned as providing an information transfer capacity of approximately 150 Mbit/second. This rate is chosen to provide a minimally sufficient bandwidth at a subscriber interface to simultaneously carry a broadband video service, such as high definition video, and various narrowband services, such as voice transmission. In addition, B-ISDN is also expected to serve as a high speed data transport facility for interconnecting separate local area networks (LANs). Presently, Ethernet based and many other types of LANs generally operate at a gross bit rate of approximately 10 Mbit/second. A proposed LAN, the Fiber Distributed Data Interface, is expected to operate at a gross bit rate of 125 Mbit/second. With this in mind, a bandwidth of 150 Mbit/second currently appears to be sufficiently fast to satisfactorily interconnect a wide variety of different LANs, encompassing those that are currently in use to many of those that are presently being proposed. Furthermore, B-ISDN must also fully accommodate relatively slow ISDN traffic, such as that which occurs at the basic rate. ISDN involves a marriage of two different transport and switching technologies: circuit switching and packet switching. Circuit switching inherently involves continuously maintaining a real time communication channel at the full channel bandwidth between two points in order to continuously carry information therebetween throughout the duration of a call. Owing to this inherent characteristic, circuit switching can not efficiently accommodate bursty traffic and, for this reason, is generally viewed in the art as being ill suited for use in B-ISDN. Specifically, communication for many services that will occur at relatively low information transfer rates in a B-ISDN environment will appear as periodic bursts when transported over a B-ISDN subscriber channel. In addition, high speed data, such as that occurring over a LAN interconnection, will itself be bursty even apart from the channel. Bursty communications do not require full channel bandwidth at all times. Whenever a circuit switched connection is used to carry bursty traffic, available communication bandwidth that is dedicated to carrying data that occurs between successive bursts, i.e. whenever there is no information to be transferred, is simply wasted. Inasmuch as bursty communications, of one sort or another, are expected to constitute a significant portion of B-ISDN traffic, the significant inefficiencies that would otherwise result from using circuit switched connections to carry bursty traffic through a communication channel generally dictate against using circuit switched connections in a B-ISDN environment. Despite the inherent limitation on carrying bursty traffic at high efficiencies over circuit switched connections, attempts are still being made in the art to adapt circuit switching to a B-ISDN environment. Nevertheless, while many advances have been and are continuing to be made in circuit switching technology, circuit switching still remains poorly adapted to supporting communication services that occur over widely diverse information transfer rates such as those which are expected to occur in B-ISDN. For example, one attempt advocates overlaying a number of circuit switching fabrics to form a network, with each different fabric operating at a transfer rate of a single prominent broad- or narrowband service. Unfortunately, if this attempt were to be implemented, then segregated switching fabrics would likely proliferate throughout the public telephone network which would disadvantageously and unnecessarily complicate the tasks of provisioning, maintaining and operating the network. Hence, this attempt is not favored in the art. Another attempt in the art aims at providing multi-rate switching. Here, a single group of allocated channels would provide information transport, with each channel providing information transport at a different multiple of a basic transfer rate. A switch would then be dynamically reconfigured, based upon each subscriber's needs, to support specific services therefor that occur at different transfer rates. Unfortunately and disadvantageously, the resulting switch would be considerably more complex than a single rate circuit switch. Furthermore, all channels in a group would need to be synchronized with respect to each other and with no differential delay occurring thereamong. Owing to the need from time to time to switch calls from one physical facility to another as required by network maintenance, maintaining the necessary intra-group synchronization is likely to be quite difficult. As such, this proposal is also not favored. In this regard, see, H. Ahmadi et al, "A Survey of Modern High-Performance Switching Techniques", IEEE Journal on Selected Areas in Communications, Vol. 7, No. 7, September 1989, pages 1091-1103 (hereinafter referred to as the Ahmadi et al publication); and J. J. Kulzer et al, "Statistical Switching Architectures for Future Services", International Switching Symposium ISS'84, Florence, Italy, May 7-11, 1984, Session 43A, paper 1, pages 1-5 (hereinafter referred to as the Kulzer et al publication). Given the drawbacks associated with circuit switched connections, packet switched connections, specifically using asynchronous transfer mode (ATM), presently appear to be the preferred mode of communication over B-ISDN. This mode involves asynchronous time division multiplexing and fast (high speed) packet switching. In essence, ATM relies on asynchronously transporting information in the form of specialized packets, i.e. so-called ATM "cells". Each ATM cell includes a header followed by accompanying data. The header contains a label, which is used for multiplexing and routing, that uniquely identifies the B-ISDN channel which is to carry that cell between two network nodes. A specific periodic time slot is not assigned to carry a cell on any B-ISDN channel. Rather, once an ATM cell reaches, for example, a B-ISDN switch, fast packet switching occurs: a route is dynamically established through the switch to an output destination for that particular cell followed by transport of the cell over that route, and so on for each successive cell. A route is only established in response to the cell reaching an input of the switch. Advantageously, ATM communication allows any arbitrary information transfer rate up to the full facility rate to be supported for a B-ISDN service by simply transmitting cells at a corresponding frequency into the network. With ATM, channel bandwidth is dynamically allocated to any B-ISDN call and simply varies with the rate at which cells for that call are applied through a B-ISDN channel. No further intervention is required by either the subscriber or the network itself to utilize differing amounts of available channel bandwidth, as the need therefor arises. Any change in that subscriber's traffic patterns or services, even if dramatic, merely results in a changing mix of cells that are presented to the network for these services and changes in their corresponding rates of occurrence. As long as sufficient bandwidth is available on any subscriber channel to carry all the cells presented thereto, the ATM switching fabric merely continues to route cells to their appropriate destinations and remains essentially unaffected by any such change. Hence, by decoupling the information transfer rates from the physical characteristics of the switching fabric and providing the capability to handle bursty traffic, ATM is particularly well suited to transporting both bursty and continuous bit rate services and is therefore preferred for B-ISDN service. In this regard, see the Kulzer et al publication. An essential ingredient of B-ISDN is an ATM switch. In order to support B-ISDN, that switch needs to possess the capability of routing cells at an information transfer rate of at least 150 Mbit/second between separate ATM ports. Based upon current estimates, a large central office B-ISDN switch is expected to handle approximately 80,000 subscriber lines each having a 150 Mbit/second channel. With a concentration ratio of 10-to-1, the switch needs to possess a total throughput of approximately 1.2 Terabit/second (1.2.times.10.sup.12 bits/second). Not surprisingly, a number of different architectures has been proposed in the art for implementing a high speed, e.g. approximately 1 Terabit/second, ATM switch. One such illustrative architecture, which has been widely used in circuit switches, involves the use of a switch that has a single squared matrix of cross-point switching elements. See, e.g. U.S. Pat. No. 4,692,917 (issued to M. Fujoika on Sep. 8, 1987). Advantageously, such switches are internally non-blocking, i.e. once appropriate connections are established for the entire matrix at any given time there will be no contention for any link within that matrix and thereby two cells will not collide therein. However, these switches do suffer from output port contention. This deficiency can be ameliorated somewhat through use of various queuing functions and/or centralized control--though at the expense of significantly increasing switch complexity and cost. More significantly, the cross-point matrix that forms the basis of such a switch has the disadvantageous property of squared growth. Given this growth function, it has been known for some time that a crosspoint matrix switch capable of serving a relatively large number of ports is extremely costly to implement. Because of the cost, the art has concluded that a single stage cross-point matrix should be used only in those instances where the packet switch is relatively small or where a relatively small cross-point matrix forms a building block of a large multi-stage switch. In this regard, see pages 1098 and 1099 of the Ahmadi et al publication as well as pages 4 and 5 of the Kulzer et al publication. In an effort to devise internally non-blocking switching architectures that utilize fewer cross-points than in a single stage crosspoint matrix, the art has devoted considerable attention to use of cascaded interconnection networks that present multi-path switching. One such illustrative architecture involves Batcher-Banyan networks. Examples of Batcher-Banyan based packet switch architectures can be found in the following United States patents, all of which are assigned to the present assignee hereof: U.S. Pat. No. 4,910,730 (issued to C. M. Day et al on Mar. 20, 1990--hereinafter referred to as the Day et al '730 patent); U.S. Pat. No. 4,893,304 (issued to J. N. Giacopelli et al on Jan. 9, 1990); U.S. Pat. No. 4,866,701 (issued to J. N. Giacopelli et al on Sep. 12, 1989); U.S. Pat. No. 4,817,084 (issued to E. Arthurs et al on Mar. 28, 1989); U.S. Pat. No. 4,761,780 (issued to B. L. Bingham et al on Aug. 2, 1988); and in the following publications: J. N. Giacopelli et al, "Sunshine: A High performance Self-Routing Broadband Packet Switch Architecture", Proceedings of the XIII International Switching Symposium 1990, Stockholm, Sweden, Paper 21, Vol. III, pages 123-129; T. T. Lee, "A Modular Architecture for Very Large Packet Switches", Proceedings of IEEE Globecom '89, Dallas, Tex., November 1989, pages 1801-1809; and Hui et al, "A Broadband Packet Switch for Integrated Transport", IEEE Journal on Selected Areas in Communications, Vol. SAC-5, No. 8, October 1987, pages 1264-1273. In general, in a Batcher-Banyan based switch, all incoming cells are first routed through a single Batcher sorting network which, in turn, feeds a Banyan routing network. The Batcher network first sorts all simultaneously occurring incoming ATM cells into an ascending order, after which the Banyan routing network routes each of these cells to its addressed destination output port of the switch. Each network is formed of multiple columns of identical Batcher sorting circuits or identical Banyan routing circuits thereby forming respective multi-stage Batcher or Banyan networks. These columns are internally interconnected within each network by binary wiring patterns. Each individual Batcher and Banyan circuit typically has two separate inputs and two separate outputs. A Batcher network may be interconnected to a Banyan network using a so-called "perfect shuffle" wiring pattern. Incoming ATM cells typically include a header which includes an activity bit followed by address bits. In operation, the Batcher network sorts the incoming cells into ascending order based upon serial comparisons of their destination addresses. In response to these comparisons, each Batcher circuit receives two cells simultaneously and assumes either a pass state or a cross state for these two cells. If a Batcher circuit assumes a pass state, then the two cells that are presented to two inputs of that circuit simultaneously appear on corresponding outputs thereof. Alternatively, if that circuit assumes a cross state, then those cells simultaneously appear on the opposite outputs of that circuit. Various Batcher circuits are configured to route that one of the two cells having a higher address to an upper output of each such circuit, while the remaining Batcher circuits are configured to route such cells to the lower output. Similarly, each Banyan circuit decides whether to assume a pass or cross state. However, in lieu of comparing cell addresses as occurs in each Batcher circuit, each Banyan circuit forms its decision for any given cell presented to that circuit based upon the activity bit, to determine cell validity, and a single address bit in that cell. Each Banyan circuit situated in successive stages of the Banyan routing network serially rotates the address of each incoming cell applied to that circuit by one bit position and then utilizes what is then the most significant bit of the rotated address in forming its decision. Hence, the first column of Banyan circuits operates on the most significant bit of the output port address for each incoming cell applied to the Banyan routing network, while the last column of Banyan circuits operate on the least significant bit of that address. Other cascaded switch architectures, such as Clos and Benes type networks, that have been proposed in the art rely on using several successive serially connected routing stages, with each stage being implemented using a bus, ring or a shared memory structure. Unfortunately, the routing algorithms that must be followed in these switches to avoid blocking tend to be complex and generally require examining the state of the entire switch before routing decisions can be made. In this regard, see pages 4 and 5 of the Kulzer et al publication. Consequently, these other switch architectures, as presently proposed, are also not suitable for use in implementing an ATM switch for actual B-ISDN service. In addition, while Batcher-Banyan and other packet switches that rely on cascaded architectures utilize far fewer individual switching circuits than does a crosspoint matrix switch, such cascaded packet switches possess various faults which severely limit their incorporation into an actual operating telephone network. First, because these switches possess highly efficient switching topologies, these switches generally have insufficient redundancies and thereby exhibit very poor fault tolerance. In the event that a single switching circuit in such a packet switch, such as illustratively that described in the Day et al '730 patent, fails, then typically, due to an inherent inability within the switch to route packets around that particular circuit, the entire switch will need to be taken out of service for a period of time during which the fault would be isolated and repaired. Thus, to provide adequate levels of fault tolerance which sufficiently avoid impairments or, in extreme cases, disruption of network switching capacity, the entire cascaded switch might need to be duplicated, with both switches operating, for example, on a well known "hot-standby" basis. Unfortunately, this is an extremely costly solution and hence one that is quite impractical. Second, cascaded switches are extremely difficult to expand. Ordinarily, a basic sized switch is first installed in a network and, as the need arises, is "grown" by successively adding pre-defined increments of switching fabric to continually increase the capacity of that switch in a manner that keeps pace with increasing subscriber demands for services. Unfortunately, the topology of a cascaded switch architecture does not lend itself to incremental growth. In this regard, due to the inflexibility of the switching topology, increasing the size of a cascaded switch generally necessitates a complete re-design and/or replacement of the switching fabric. Hence, a cascaded switch must be initially sized to carry the full switching load that will be expected to occur during its useful life. As such, a local telephone company might likely be faced with significant entry costs in providing B-ISDN service if it were to provide this service through such a cascaded switch. Moreover, the steady state subscriber demand for packet services, specifically B-ISDN, is extremely difficult to estimate, within an acceptable margin of error, prior to the deployment of the services. Accordingly, this difficulty injects sizeable uncertainties into the design and costing of such a switch. Lastly, the high density and complexity of the inter- and intra-switching module interconnect wiring used in a cascaded switch complicates the design of such a switch. It also reduces the physical space that would otherwise be available within a custom integrated circuit(s) for integrating the physical components that are needed to implement each separate switching (e.g. Batcher or Banyan) circuit. Accordingly, by artificially reducing the integration density of the switching circuits used in a cascaded switch, the physical volume and component count of the entire switch both tend to increase thereby again disadvantageously increasing the cost of the switch. Thus, a need exists in the art for a large, e.g. at least 1 Terabit/second, packet switch particularly suited for use with ATM communication that is relatively inexpensive and simple to implement when compared to packet switches of similar capacity that have been proposed in the art. In addition, the needed packet switch should exhibit a high degree of fault tolerance and be readily and economically expandable on an incremental basis. Advantageously, the emergence of such a switch could well facilitate the provision and deployment of B-ISDN service throughout the public telephone network. SUMMARY OF THE INVENTION The inventive large capacity packet switch substantially eliminates the deficiencies associated with such switches known in the art, including those proposed for transport of ATM cells. In particular, the inventive architecture utilizes a series of "k" separate identical input modules, each of which provides incoming ATM cells from "n" separate input ports to "m" separate identical self-routing cross-point planes. Each of the cross-point planes possesses a k-by-k switching capacity and routes incoming ATM cells to each one of "k" separate output modules. Each output module services "n" separate output ports. With "n", "m" and "k" illustratively equalling the values 32, 32 and 256 respectively, the inventive switch provides an 8192-by-8192 capacity. Each ATM cell possesses a header containing a virtual channel identifier (VCI) field and a priority field. The VCI field specifies the specific virtual channel through the switch that is to carry that cell. Upon arrival at an appropriate interface module, the VCI field of each ATM cell is read, translated and over-written with a VCI value that specifies the specific virtual channel that is to carry that cell between the switch and a downstream node on the B-ISDN network. In addition, the interface module also prepends a routing header to each incoming ATM cell. This prepended routing header, used solely within the switch, contains fields which specify a physical output module address and a specific output port address on that output module to which that cell is destined. Each input module in the inventive switch has a single internal queue, illustratively implemented using shared memory, and services "n" separate input ports. All the input ports serviced by this module are sequentially read in a round-robin fashion with the incoming ATM cell incident on each input port being deposited in next successive location in the queue. Inasmuch as multiple incoming ATM cells can address the same output module and thus cause output port contention, all "k" input modules simultaneously send the address and accompanying priority information for the cells situated at the heads of their internal queues to a centralized contention resolution unit to determine, through arbitration, which ones of these cells can then be simultaneously routed through a common cross-point plane. Those cells that lose arbitration remain at the head of their respective queues for processing during the next round of arbitration. Those cells that win arbitration are simultaneously applied by their respective input modules through the cross-point switching planes and routed therethrough to the addressed output modules for each of these cells. Each output module contains "n", illustratively 32, separate logical queues and is connected to the same one of the "k" different outputs on each of the "m" different cross-point planes. These queues are also implemented using illustratively shared memory. The input lines on each output module are sequentially read in a round-robin fashion. Based upon the output port address within each incoming ATM cell present on these input lines, that cell is then deposited at the end of a corresponding internal queue for that output port. These internal queues are read in a round-robin fashion with the ATM cell situated at the head of the queue being supplied in bit serial fashion, though without its prepended routing header, to a corresponding output port. To provide an approximate 1 Terabit/second data rate, an inventive technique has been developed for operating all the cross-point switching planes on a parallel, though time staggered (phased), basis. Specifically, the inventive technique relies on dividing an STS-3c cell period, which is approximately 2.83 .mu.sec, into "m", illustratively 32, separate successive "staggered" time intervals. During each such staggered time interval, such as the first interval, every input module simultaneously provides output port address and cell priority information (collectively referred to as a "request") for the ATM cell presently situated at the head of its internal queue to the contention resolution unit. Thereafter, again during this interval, the contention resolution unit performs a complete arbitration cycle through which it compares the current request received from every input module to every other such current request received from all the other input modules that are being presented during this interval. Using top-down physical ordering modified by fairness and cell priority considerations, the contention resolution unit resolves contending requests and provides appropriate signals to all the input modules specifying which of these modules have presently won arbitration. In response to these signals, all the input modules that have won arbitration during, for example, the first staggered time interval then simultaneously route, on a serial basis, the ATM cells situated at the head of their internal queues onward through a specific cross-point plane, e.g. the first such plane, during the remainder of an STS-3c cell period, to the addressed output modules. This process then repeats one staggered time interval later, e.g. during the second time interval, but with the ATM cells that have won arbitration during this second staggered time interval being serially routed through the next successive cross-point switching plane, e.g. the second plane, and so on, for the remainder of the cross-point planes. Those ATM cells that have not won arbitration during any one staggered time interval remain at the head of each of their corresponding queues and await contention resolution and routing during the next successive staggered time interval. Thus, a separate group of upwards of 256 ATM cells is launched into all 32 cross-planes every staggered time interval, i.e. every 2.83/m .mu.second, with each cross-point plane itself routing therethrough upwards of the 256 separate ATM cells that comprise such a group during every STS-3c cell period, i.e. every 2.83 .mu.sec. Although all the cross-point switching planes operate in the same identical fashion, each of these planes operates on a staggered (phased) basis with respect to its neighboring planes, by routing a group of ATM cells therethrough commencing either 2.83/m .mu.sec before or after that of its neighboring planes. Fast contention resolution permits all the cross-point switching planes to be operated in parallel. Advantageously, this permits the switch to possess an architecture that is both compact and modular. Furthermore, an inventive technique, illustratively for use in the switch, has been developed that substantially reduces the amount of time required to configure all the cross-point planes prior to routing a group of cells therethrough. This technique, which we refer to as cell address "look-ahead", relies on storing configuration information within each cross-point circuit, in every cross-point switching plane, one cell in advance of the actual cell that is being routed therethrough. Specifically, the prepended routing header for each ATM cell that is applied to each input of every cross-point switching plane contains the output module address of the next successive ATM cell that will be applied to that specific input. Each individual cross-point circuit situated within each switching plane has an accompanying one-bit register that stores the "future configuration" of that circuit. While a group of individual ATM cells is being serially shifted into the inputs of a cross-point plane, the prepended routing headers for these cells are used to set the "future configuration" bit within all the individual cross-point circuits for each input line thereto. Then, after that group of cells has been completely routed through the cross-point plane, a strobe pulse is applied to all the cross-point circuits within that plane to simultaneously set the switching configuration of all those circuits to that specified by the stored future configuration bits, thereby essentially instantaneously setting the entire plane to properly route the next group of cells that will be switched therethrough, and so on for each successive cell on every input to each cross-point plane. Owing to the high degree of parallelism inherent in this technique, the time required between successive routing operations to change the configuration of the entire cross-point switching matrix is advantageously reduced to essentially only a very short interval required to "strobe" the future configuration into the cross-point circuits. Inasmuch as the entire switch configuration is stored in parallel with the cell routing operations rather than being undertaken sequentially prior thereto, switching bandwidth is advantageously increased. Furthermore, storing the future configuration in advance of the corresponding cells, through use of the inventive cell address "look ahead" technique, significantly relaxes a relatively tight time constraint that would otherwise exist for reading the prepended routing header of each of the current cells and then setting the switch configuration therefor. As a result, the need to employ relatively costly high speed logic to read the prepended routing headers and set the configuration of all the cross-point circuits. Thus, ATM cells are routed on a distributed basis through the inventive switch, i.e. in parallel through input and output modules and cross-point switching planes, while switch control, including contention resolution, is provided on a centralized basis. Due to the use of distributed routing, the inventive switch is significantly less complex and less costly to implement than designs for high speed packet switches, particularly those for ATM service, known in the art. Advantageously, a matrix of cross-point elements has not only proven in the past to be very reliable under actual service conditions, but also due to its intrinsic redundancies, possesses the capabilities of being internally non-blocking and able to dynamically isolate a number of separate switching elements from active service without significantly affecting the throughput of the entire switch. Moreover, the inventive crosspoint matrix based switch architecture can be easily and relatively inexpensively grown, within reasonable limits, by merely adding additional switching fabric to the matrix. Furthermore, the interconnect wiring in the inventive crosspoint matrix based switch tends to be significantly less complicated and requires much less volume both within and among custom integrated circuits used to fabricate the switching fabric than that required in a cascaded switch architecture, thereby reducing the physical size requirements for the entire switch as well as its cost. In accordance with a feature of the invention, the number of cross-point planes grows in a linear, not squared, fashion as the number of input and output ports increases. Such a growth path is less expensive than the squared growth path associated with various packet switch designs known in the art. The invention also provides the feature of possessing a small failure group size in the event of a failure of an input or output module. In this respect, such a failure in a switch serving, for example, 8192 input and 8192 output ports will only affect 32 input or output ports, respectively (less than 1% of the total switch capacity), rather than causing the entire switch to fail as occurs with various ATM switch designs known in the art. Moreover, the inventive switch can be easily re-configured to route ATM cells around a failed input or output module without the need to restart call processing. By employing at least one spare input module, one spare output module, "k-1" active input modules and "k-1" active output modules, the inventive switch is robust and provides a very high degree of fault tolerance. In addition, fault tolerance can be increased by triplicating the contention resolution unit and adding inexpensive majority voting logic to process the outputs thereof. Furthermore, a failure of a previously operational cross-point switching plane will only reduce switch capacity by approximately 3.1% which is generally low enough to be completely absorbed by the excess operating capacity intentionally designed into the switch with little, if any, adverse effects on the B-ISDN traffic currently being handled thereby. BRIEF DESCRIPTION OF THE DRAWINGS The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 shows a typical ATM cell, and its constituent fields, as transported through the inventive packet switch; FIG. 2 is a high level block diagram of a preferred embodiment of a broadband ISDN switch constructed in accordance with the teachings of the invention; FIG. 3A is a block diagram of a typical interface module, illustratively module 210.sub.1, shown in FIG. 2; FIG. 3B is a block diagram of a typical header processing unit, illustratively unit 310.sub.1, shown in FIG. 3A; FIG. 4 is a high level flowchart of Routing Header Prepending and VCI Translation Routine 400 undertaken by processor 360 in header processing unit 310.sub.1 shown in FIG. 3B; FIG. 5 is a block diagram of switch fabric 250 which is shown in FIG. 2 and which is constructed in accordance with the inventive teachings; FIG. 6 is a timing diagram of inventive staggered routing and contention resolution operations that occur within switch fabric 250; FIG. 7 (shows the relationship between successive ATM cells that are applied to any one input of a cross-point switching plane located within switch fabric 250 and their associated routing headers prepended in accordance with the teachings of the present invention; FIG. 8 is a high level block diagram of a typical cross-point switching plane, illustratively plane 550.sub.1, shown in FIG. 5; FIG. 9A is a block diagram of a portion of a first embodiment of a typical single self-routing cross-point circuit, illustratively circuit 800.sub.1 shown in FIG. 8, that cen be used within each cross-point plane in the inventive broadband ISDN switch; FIG. 9B is a block diagram of a portion of a second embodiment of a typical single self-routing cross-point circuit, though of the same corresponding portion as shown in FIG. 9A of illustratively circuit 800.sub.1 shown in FIG. 8; FIG. 10 is a block diagram of a typical input module, illustratively input module 260.sub.1, shown in FIGS. 2 and 5; FIG. 11 is a block diagram of a typical routing header transfer circuit, illustratively circuit 1080.sub.1, shown in FIG. 10; FIG. 12 is a block diagram of a typical output module, illustratively output module 270.sub.1, shown in FIGS. 2 and 5; FIG. 13 is an overall high level functional block diagram of contention resolution unit 510 shown in FIG. 5; FIG. 14 depicts a register diagram showing the contents of registers R, S and T shown in FIG. 13 at the beginning of an arbitration cycle and after the first and second shift cycles; FIG. 15 is a high level block diagram of a preferred embodiment of contention resolution unit 510 as it would be typically implemented in practice; FIG. 16 is a block diagram of a typical contention resolution circuit, illustratively circuit 1512.sub.1,1, used within the implementation of the contention resolution unit 510 shown in FIG. 15; FIG. 17 is a high level block diagram which shows the use of redundant contention resolution and majority voting; FIG. 18 is a simplified block diagram of the inventive broadband ISDN switch which specifically shows packet re-routing around a failed input or output module; FIG. 19 shows the proper alignment of the drawing sheets for FIGS. 19A and 19B; FIGS. 19A and 19B collectively depict a high level flowchart of Fault Recovery Process 1900 which is executed by switch control module 290 in the event of a failure in an input or output module or in a cross-point switch plane; and FIG. 20 is a block diagram of an alternate embodiment of the inventive broadband ISDN switch, particularly switch fabric 250, which utilizes a fiber optic interconnect to and from the cross-point switching planes. To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. DETAILED DESCRIPTION After considering the following description, those skilled in the art will clearly realize that the teachings of the invention can be readily utilized in implementing nearly any packet switch of essentially any size, up to that imposed by technological speed limitations regardless of whether that switch is to be used for service in ISDN (Integrated Service Digital Network) or not. Furthermore, the inventive teachings can be used in such a switch that accommodates packets of nearly any size and transmission period. Nevertheless, for purposes of illustration and to simplify the ensuing description, the invention will be specifically discussed in the context of a 8192-by-8192 port packet switch particularly suited for switching asynchronous transport mode (ATM) packets which are applied to each input of a broadband ISDN (B-ISDN) switch at a rate of 155.52 Mbit/second (STS-3c rate). The period during which an ATM packet occurs (i.e. the "packet period") is approximately 2.83 .mu.sec. A. Basic ATM Cell Structure Broadband ISDN relies on transporting individual packets of digital data through a packet network situated between user terminals. To provide data carriage for a sufficient number of services, including high definition video, a broadband ISDN user is to be provided with an STS-3c bit rate data channel. Such a channel has a total throughput of 155.52 Mbit/second and an effective data throughput, excluding overhead bits, of 149.76 Mbit/second. Each broadband ISDN packet is commonly referred to as a "cell". FIG. 1 shows a typical ATM cell, and its constituent fields, both as supplied by a broadband ISDN terminal and subsequently transported through the inventive packet switch. As shown, incoming ATM cell 110, typically 53 bytes long, is formed of header 115, itself containing virtual channel identifier (VCI) field 116 and priority field 117, followed by all remaining bits. These bits, which are collectively labelled as data 113, are the so-called "user data" bits and are merely transported unchanged through the switch. On an STS-3c line, a 53 byte ATM cell is typically delivered every 2.83 .mu.sec (which is the "cell period"). The VCI identifies a specific virtual channel that is to transport the cell and which extends between a node within the B-ISDN network to the next successive such node. The specific channel and hence its corresponding VCI varies from one node to the next as the cell is transported through successive network nodes. The value of priority field 117 is determined during call set-up negotiations and, as a result, is appropriately set by the user terminal that initially produced cell 110. This value specifies the priority, relative to that associated with other cells, at which the cell is to be transported through the B-ISDN network. The value of the priority field remains constant as the cell propagates through the network. As will be described in much detail below, the inventive switch is self-routing. This means that, prior to a cell being launched into the network, a route for a cell does not need to be extended through the network including all the switches therein. In fact, with self-routing switches, information stored within each cell itself is used to form a route through each switch whenever that cell reaches that switch. In this regard, the inventive switch, in a manner to be described below, translates the VCI of each incoming cell into a new VCI (to identify an output virtual channel from the switch) and prepends thirteen-bit routing header 120 to that cell. The routing header is strictly for internal use in routing the entire cell through the inventive switch. The routing header, indicated by dotted lines, is prepended to each such cell prior to entry of that cell into the inventive switch and is subsequently stripped off that cell prior to that cell being transmitted into the output virtual channel. As shown in FIG. 1, routing header 120 contains two fields: most significant five-bit "H" field 123, that specifies a physical address (1 out of 32) of a specific output port on an output module to which that cell is destined within the inventive switch, preceded by a least significant eight-bit "L'.revreaction. field 127 which provides a physical address (1 out of 128) of the specific output module to which the cell is destined. Within the switch, cell 110 is treated simply as data and provided with bit-serial transport therethrough. The resulting ATM cell, including the prepended routing header that is transported through the inventive switch, is denoted by reference numeral 100. B. Overall Architecture of the Inventive B-ISDN Switch FIG. 2 is a high level block diagram of a preferred embodiment of broadband ISDN switch 200 constructed in accordance with the teachings of the invention. For purposes of simplification, various control and clocking signals and associated circuit blocks that would be readily apparent to those skilled in the art have been intentionally omitted from this and other figures. As shown, the inventive switch is basically formed of interface modules 210, control and service modules 295, cross-connect 220, demultiplexors 230, multiplexors 280, switch fabric 250 and switch control module 290. Interface modules 210 consisting of identical modules 210.sub.1, 210.sub.2, 210.sub.3, . . . 210.sub.j interface a number of user lines 205, specifically corresponding user line groups 205.sub.1, 205.sub.2, 205.sub.3, . . ., 205.sub.j to switch 200. User terminals (well known and not shown) are connected to the far end of each of these user lines and supply incoming ATM cells in bit-serial fashion thereto and receive outgoing ATM cells therefrom. In essence, each of the interface modules provides a number of essential network functions: it terminates each of its associated data lines, whether emanating from a user or the network; it protects the B-ISDN network both physically (electrically) and in terms of maintaining incoming data in an appropriate form suitable for carriage through the network; it provides a policing function by, for example, limiting the data rate (channel bandwidth) accorded to a user to that which the user has specifically contracted; it concentrates and sorts incoming packets, as needed; and, as discussed in detail below, it performs cell header translation for each incoming ATM cell and prepends a routing header to each such cell. Through appropriate leads within leads 215, each interface module bi-directionally communicates with the remainder of switch 200 by providing incoming cells at an STS-48 rate (16 times the basic STS-3c rate or approximately 2.488 Gbit/second) and receiving outgoing cells at the same rate. Each of the interface modules is connected to switch control module 290 through leads 293 and is appropriately monitored and controlled thereby. Under the control of switch control module 290, control and service modules 295, provide, also through appropriate leads within leads 215, special purpose inputs and outputs, such as for packet test and switch operations and maintenance connections, into switch 200. Generally speaking, switch control module 290 performs a number of essential control, test and administration functions for switch 200. To effectively perform these functions, switch control module 290, over leads 293, bi-directionally communicates with and controls each of the blocks that constitutes switch 200 including interface modules 210, cross-connect 220 and switch fabric 250. For example, switch control module 290 processes incoming calls by establishing and tearing down appropriate virtual connections through switch 200 for each such call, selecting routes through cross-connect 220 for incoming and outgoing ATM cells that constitute each call handled by switch 200, and by determining the specific header translation that is to occur within each interface module. In addition, the switch control module also performs network maintenance and administrative functions by respectively attempting to locate and repair problems within the network itself and maintaining data on the performance and status of switch 200 and its interactions with the network. Switch control module 290 also distributes traffic between switch 200 and the remainder of the network in order to efficiently use existing network resources. In addition, module 290 also responds to various user inquiries as well as to user requests to change service. Switch control module 290 also performs periodic routine diagnostic tests of the entire switch. In particular, switch control module 290 periodically executes a sequence of diagnostic operations to apply pre-defined ATM test cells to and test the resulting operation, on an end-to-end basis, of the entire switch as well as to test the operation of each of the blocks, as set forth above, within both the switch and the switch fabric. Through these diagnostics, switch control module 290 is able to detect failure conditions and, in the event of such a failure, invoke appropriate corrective action to counteract the failure. The corrective action taken in response to a failure of a cross-point switch plane, an input module or an output module is discussed in detail below. Switch control module 290 is formed of any one of many well-known relatively large stored programmed computers and associated peripheral and memory circuits. Cross-connect 220 is a computer controlled switching matrix that provides circuit switched connections between lines 215, which are connected to interface modules 210 and control and service modules 295, and lines 225. The connections through the cross-connect are established by switch control module 290 and are dynamically changed, as needed, in the event of a failure within switch fabric 250 (specifically of an input or output module, as discussed in detail below) to provide fault tolerant B-ISDN switching operation. High speed trunks, connected through appropriate specialized interface modules would link switch 200 to other switching nodes situated within a B-ISDN network. Since these trunks are irrelevant to the present invention, they have been omitted from the drawing. Lines 225 apply incoming cells at the STS-48 rate to demultiplexors 230 and accept outgoing cells also at the STS-48 rate from multiplexors 280. Demultiplexors 230, which are formed of identical individual demultiplexors 230.sub.1, 230.sub.2, . . . , 230.sub.1-1, 230.sub.1, demultiplex the cells occurring at the STS-48 rate and appearing on single incoming lines, on a 1-to-16 basis, into separate bit-serial lines 245 at the STS-3c rate. Similarly, outgoing cells provided by switch fabric 250 over lines 275 at an STS-3c rate are multiplexed, on a -16-to-1 basis, into single STS-48 outgoing lines situated within lines 225 by multiplexors 280 formed by identical individual multiplexors 280.sub.1, 280.sub.2, . . . 280.sub.1-1, 280.sub.1. Incoming STS-3c lines 245 are connected to identical input modules 260 located within the switch fabric and specifically to corresponding input modules 260.sub.1, . . . , 260.sub.k. Switch fabric 250 also contains output modules 270, contention resolution unit 510 and self-routing cross-point planes 550. As described in detail below in conjunction with FIG. 5, the input modules provide groups of simultaneous incoming cells to self-routing cross-point planes 550 for simultaneous routing therethrough. Switching planes 550 are formed of multiple planes of self-routing cross-point circuits. Cross-point connections are used because this type of connection is internally non-blocking and has proven to be highly reliable under actual operating service. The input modules, in conjunction with contention resolution unit 510, select appropriate cells from the input ports, which are fed by lines 245, for carriage through planes 550 in order to eliminate the occurrence of output contention, i.e. two or more cells attempting to simultaneously reach same specific output port within output modules 270. Outgoing cells conducted through planes 550 are directed to output modules 270 which are themselves formed of identical individual output modules 270.sub.1, 270.sub.2, . . . , 270.sub.k. Each of the output modules directs each of the outgoing cells received by that module, but without the accompanying routing header, to one of 32 appropriate output ports on that module. Each of these ports is connected via an outgoing STS-3c line within output lines 275 to multiplexors 280 and therethrough to cross-connect 220 back to either a user line or a high speed link to another network switch. C. Interface Module and Header Processing Unit As noted above, each interface module performs several essential functions. As it relates to the present invention, each interface module concentrates incoming ATM cells on a 10-to-1 basis and for each such cell performs cell header translation and prepends a routing header thereto. FIG. 3A is a block diagram of a typical interface module, illustratively module 210.sub.1, shown in FIG. 2. This module contains header processing units 310, 10-to-1 concentrator 317, multiplexor 320, 1-to-10 expander 332 and demultiplexor 330. Each interface module concentrates incoming ATM cells appearing on 160 incoming user lines into 16 separate STS-3c lines and then multiplexes the cells appearing on these lines on a 16-to-1 basis into one multiplexed STS-48 trunk, which, in turn, is connected to an input of cross-connect 220. Similarly, but in a reversed fashion, each interface module also demultiplexes an outgoing STS-48 line from cross-connect 220, on a 1-to-16 basis, into 16 separate STS-3c lines 323 and further expands each of these STS-3c lines, on a 1-to-10 basis, to yield a total of 160 separate user lines 335. Accordingly, interface module 310.sub.1 serves incoming user lines 305.sub.1, . . . , 305.sub.160 and outgoing user lines 335.sub.1, . . . , 335.sub.160 which collectively form user lines 205.sub.1. Each user is provided with both an incoming and an outgoing user line, e.g. lines 305.sub.1 and 335.sub.1. The incoming and outgoing STS-48 lines served by module 210.sub.1 form leads 215.sub.1. Each incoming user line is connected to a corresponding header processing (HP) unit located within units 310, specifically formed of header processing units 310.sub.1, . . . , 310.sub.160 respectively associated with lines 305.sub.1, 305.sub.160. All of the header processing units are identical. As discussed in detail below in connection with FIG. 3B, each header processing unit translates the current VCI of an incoming ATM cell into a new VCI value for transport to the next successive node in the network, overwrites the current VCI field with the new VCI field (though maintaining a priority field at its prior value) and appends an appropriate routing header to that cell for internal use by switch fabric 250 in routing the cell therethrough. The outputs provided by header processing units 310 are routed over serial leads 315 formed of individual lines 315.sub.1, . . . , 315.sub.160 for units 310.sub.1, . . . , 310.sub.160, to concentrator 317. The concentrator concentrates the cell traffic appearing on every group of 10 successive user lines into one corresponding STS-3c line thereby providing incoming STS-3 c lines 319 formed of individual lines 319.sub.1, . . . , 319.sub.16. Lines 319 are routed to multiplexor 320, which, through time division multiplexing, multiplexes the cell traffic appearing on these sixteen STS-3c lines onto one STS-48 line that feeds cross-connect 220. Leads 337 (which form a portion of leads 293 shown in FIG. 2) connect each of the header processing units to switch control module 290 for use in transferring data to the switch control module and receiving control instructions and accompanying data therefrom, as discussed in detail below. The outgoing STS-48 line is applied to demultiplexor 330 which, in turn and through time division demultiplexing, demultiplexes the cell traffic on this line across 16 separate STS-3c lines 323, which are formed of individual outgoing STS-3c lines 323.sub.1, . . . , 323.sub.16. Outgoing lines 323 are applied as input to expander 332 which, in turn, expands each such line into 10 successive corresponding user lines, thereby providing outgoing user lines 335.sub.1, . . . 335.sub.160 which collectively form a portion of user lines 205.sub.1. Both concentrator 317 and expander 332 are well known in the art. FIG. 3B is a block diagram of a typical header processing unit, illustratively unit 310.sub.1, shown in FIG. 3A. As discussed above, for each incoming ATM cell, this unit translates the current VCI field for that cell into a new VCI, over-writes the current VCI with the new VCI and prepends an appropriate routing header onto that cell. As shown, header processing unit 310.sub.1 is formed of input buffer 340, output buffer 350, processor 360 and memory 370. The input and output buffers are connected through respective leads 363 and 355 to processor 360 which itself is connected through leads 365 to memory 370. Each of these buffers provides a one cell delay. The incoming one cell delay through the header processing unit provides processor 360 with sufficient time to perform table look-up operations (as described in detail below in conjunction with FIG. 4) into memory 370, as shown in FIG. 3B, to translate the current VCI for an incoming cell and formulate an appropriate routing header for that cell. The bits shifted out of buffer 340 are shifted into output buffer 350 and therethrough onto lead 315.sub.1. However, immediately prior to the occurrence of any bits being shifted into buffer 350 from buffer 340 for an incoming ATM cell, processor 360 serially applies at the proper bit intervals appropriately valued bits over leads 355 into output buffer 350 in order to first append the routing header to this cell. Thereafter, as bits for this cell are then shifted into buffer 350, the processor serially applies appropriately valued bits, also via leads 355, to an input of buffer 350 to over-write the VCI field for this cell with a new value. Then, to complete each such cell, all the remaining bits, specifically data bits 113 (see FIG. 1) that form that cell are merely shifted into output buffer 350, as shown in FIG. 3B, in bit-serial fashion over lead 345 from the input buffer 340. The bits shifted out of buffer 350 are applied in bit-serial fashion over lead 3151 to an input of multiplexor 320. As such, each header processing unit imparts a two cell delay to each incoming ATM cell. Inasmuch as an STS-3c cell period is approximately 2.83 .mu.sec, this delay amounts to approximately 5.66 .mu.sec. Header processing unit 310.sub.1 communicates with switch control module 290 via lead 337.sub.1 which is contained within leads 337 shown in FIG. 3A. FIG. 4 is a high level flowchart of Routing Header Prepending and VCI Translation Routine 400 undertaken by processor 360 in header processing unit 310.sub.1 shown in FIG. 3B. As one can readily appreciate, this processor also executes a number of other routines related to other functions that are performed by the header processing unit. Inasmuch as these functions are only marginally relevant to the present invention and since the appropriate routines for these functions would all be readily apparent to those skilled in the art, then, for purposes of simplicity, only general mention will be made hereinafter of the other functions provided by the header processing unit, as they relate to the present invention. Now, specifically with respect to routine 400, execution proceeds to block 410 upon entry into the routine. This block, when executed, reads the value of the current VCI for the incoming ATM cell as that cell is being shifted into input buffer 340. Once the current VCI field has been completely read, execution proceeds to block 420. This block, when executed, performs a look-up operation into a table stored within memory 370. For each incoming VCI value, this table stores a new VCI value, based upon the interconnection topology of the entire B-ISDN network, and an accompanying routing header. As such, the table look-up operation results in an accessed new VCI value and an accessed routing header. Should the network interconnection topology change, header processing unit 310.sub.1 can load appropriate VCI values reflecting the changed topology into the table in response to appropriate instructions and data received over leads 293 (see FIG. 2 and specifically over lead 337.sub.1 shown in FIG. 3B) from switch control module 290. The accessed routing header contains a physical "H" address portion, i.e. a physical address of a specific output port on an output module, and a logical "L" portion, i.e. a logical address of a desired output module. Alternatively, the VCI value can be translated using direct memory addressing wherein the incoming VCI value is used as a memory address to a new VCI value, or through a content addressable memory in which the incoming VCI value is used as a "tag" value to provide an index to a location within the memory where the new VCI value is stored. Next, to provide fault tolerance, the logical address is translated into a physical module address ("L'.revreaction.) by execution of block 430 shown in FIG. 4. This translation is undertaken using a separate table of logical-to-physical (L-to-L') module addresses which is also stored within memory 370. The physical module address is used within the routing header with the correspondence between a logical address and its accompanying physical address being dictated by the status of all the individual output modules in the switch. In this regard, if any output module should fail, the switch control module can change the eight-bit physical "L'" address associated with that output module and stored in the logical-to-physical translation table without affecting the stored network topology. This has the subsequent effect of appropriately changing the prepended routing headers. To assure that no subsequent ATM cells are directed to the failed output module, the tables in all the header processing units would be simultaneously changed, typically in response to an instruction broadcast over leads 337, shown in FIG. 3A, by switch control module 290 to all these units, in the event of such a failure. By separating the VCI and L-to-L' translation tables, this advantageously helps to prevent the network data and overall network operation from being inadvertently corrupted in the event of a malfunction occurring in response to a local failure of an output module and also simplifies the manner through which an output module fault condition is handled. After block 430, shown in FIG. 4, has been executed to access a physical module address ("L'"), execution proceeds to block 440. This latter block serially applies a routing header formed of physical module address L' and physical output port address H to output buffer 350 at the proper bit times to prepend a routing header onto the head of the incoming ATM cell which is being shifted therein. Thereafter, execution passes to block 450. This block, when executed, shifts the remainder of the incoming ATM cell, in bit-serial form, from input buffer 340 into output buffer 350 and therethrough onto lead 315.sub.1 but, in the process of doing so, over-writes the VCI field with the newly accessed value thereof. The value of the priority field in the outgoing ATM cell is set to match the value of this field in the incoming ATM cell, thereby assuring that the ATM cell maintains the same priority as it propagates through the switch. Once block 450 has fully executed, then execution loops back, via path 460, to block 410 to process the next incoming ATM cell that is being serially applied to header processing unit 310.sub.1 and so on for subsequent such cells. D. Switch Fabric 250 1. Overall architecture and operation FIG. 5 provides a block diagram of switch fabric 250 which is shown in FIG. 2 and which is constructed in accordance with the inventive teachings. As shown in FIG. 5, the switch fabric contains input modules 260 composed of identical individual input modules 260.sub.1, 260.sub.2, . . . , 260.sub.k ; self-routing cross-point switching planes 550 composed of identical individual self-routing cross-point planes 550.sub.1, 550.sub.2, . . . , 550.sub.m ; output modules 270 composed of identical individual output modules 270.sub.1, 270.sub.2, . . . , 270.sub.k ; and contention resolution unit 510. In order to service a sufficient number of subscribers, such as approximately 82,000 user lines each having a 150 Mbit/second channel, the switch, assuming a 10-to-1 input concentration ratio, needs to possess a total throughput of approximately 1.2 Terabit/second (1.2.times.10.sup.12 bits/second). This, in turn, requires an 8192-by-8192 port switching fabric. As such, fabric 250 must accommodate 8192 separate input ports and 8192 separate output ports. With the architecture shown in FIG. 5, a switch this size can be readily implemented using 256 separate input modules and 256 separate output modules with each such module accommodating 32 separate STS-3c ports. As such, the values of "k" and "n" illustratively equal the values "256" and "32", respectively. Switching fabric 250 illustratively utilizes 32 separate self-routing cross-point switching planes, with each plane having 256 separate input and 256 separate output connections. As such, the value of "m" also illustratively equals the value "32". However, all of these values are merely illustrative as switches, whether for transporting ATM cells or other packets, of nearly any size can be readily constructed based upon the inventive architecture by choosing appropriate values of "k", "m" and "n" accordingly. To a certain extent, these values will be dictated by technological limits and system design tradeoffs, such as, for example, current integration density and physical input/output capacity of available integrated cross-point switch circuits and the density of available interconnect technology, as well as various attendant cost considerations thereof. The complexity, cost and density, of the interconnect wiring, as well as the technology used therefor, running to and from the cross-point switching planes also tends to limit the switching capacity of each plane as well as the number of such planes that are used. Inasmuch as a 32-by-32 port cross-point switch can be fabricated on a single integrated circuit using currently available technology, individual 256-by-256 port switching planes formed of a matrix of these discrete circuits can be readily constructed. In this regard, such an integrated switching circuit is illustratively discussed in M. Akata et al, "A 250 Mb/s 32.times.32 CMOS Crosspoint LSI for ATM Switching Systems", Digest of Technical Papers for the 1990 IEEE International Solid State Circuits Conference, February 1990, pages 30-31. At these capacities, a wired metallic interconnect can easily and economically be used to interconnect such switching planes to the input and output modules. It is contemplated that as integration density continues to increase as the result of subsequent continual advances in semiconductor technology, increasingly dense integrated cross-point switches will likely become available with port capacities that significantly exceed 32-by-32. This, in turn, will permit the port capacity of the individual switching planes as well as the overall capacity of the switch to advantageously increase without a significant attendant increase in physical size and/or the cost of each of these planes. Similarly, increases in integration density will also permit each of the input and output modules to accommodate an increased number of input or output ports without necessarily significantly increasing their physical size and/or cost. However, this, in turn, will require increasingly dense interconnects between each of the input modules and the switching planes and between each of these planes and each of the output modules. Nevertheless, it is also expected that accompanying advances will also be made in optical and/or metallic interconnection technology that will economically provide these interconnects at the required density. In this regard, FIG. 20, which will be discussed below, shows a block diagram of an alternate embodiment of switch fabric 250 in which an optical fiber interconnect has been substituted for the metallic interconnect used in the embodiment shown in FIG. 5. Use of such an optical interconnect advantageously reduces the interconnect density involving the switching planes and the input or output modules from 8,192 separate metallic conductors to 256 separate fibers. Returning to FIG. 5, each input module services a group of 32 separate STS-3c serial input bit streams which result from demultiplexing two STS-48 bit-serial input lines. Input modules 260.sub.1, 260.sub.2, . . . , 260.sub.k respectively service input line groups 245.sub.1, 245.sub.2, . . . , 245.sub.k. For any input module, each successive incoming line in the group is connected to a corresponding successive input port of that module. Each input module services 32 different incoming lines, thereby collectively providing, across all 256 such modules, a total of 8192 separate input ports. For example, the different lines in group 245.sub.1 are connected to inputs I.sub.1, I.sub.2, . . . , I.sub.n of module 260.sub.1, and so on for the other input modules. In addition, each of the input modules is connected to the same corresponding numerical input port on all of cross-point switching planes 550, with each successive input module feeding the same successive input (i.e. having the same numerical ranking) on all the switching planes. Specifically, the first input module, i.e. module 260.sub.1, feeds the first input of each of the 32 different switching planes. Outputs O.sub.1, O.sub.2, . . . , O.sub.m of module 260.sub.1 are connected, via leads 520 formed of individual leads 520.sub.1, 520.sub.2, . . . , 520.sub.m, to the first input, i.e. I.sub.1, of switching planes 550.sub.1, 550.sub.2, . . . , 550.sub.m. The second input module, i.e. module 260.sub.2, feeds, through leads 530 formed of individual leads 530.sub.1, 530.sub.2, . . . , 530.sub.m, the second input (I.sub.2) of each of the "m" different switching planes and so on with the last input module, i.e. module 260.sub.k, through leads 540 formed of individual leads 540.sub.1, 540.sub.2, . . . , 540.sub.m, feeding the last input, I.sub.k, of every switching plane. Accordingly, each of the 32 outputs of every input module feeds a different one of the 32 different cross-point switching planes; each of the switching planes, such as plane 550.sub.1 is connected, such as through leads 545, to the same numerical output, such as output O.sub.1, of all the input modules. Each of the cross-point switching planes feeds every output module. Using a similar interconnect pattern, each of the 256 numerical outputs on any one of the 32 switching planes feeds a common numerical input (i.e. having the same numerical ranking) on every output module. Specifically, the first switching plane, i.e. plane 550.sub.1, feeds the first input of each of 256 different output modules 270. Outputs O.sub.1, O.sub.2, . . . , O.sub.k of plane 550.sub.1 are connected, via leads 560 formed of individual leads 560.sub.1, 560.sub.2, . . . , 560.sub.k, to the first input, i.e I.sub.1, of all the output modules 270.sub.1, 270.sub.2, . . . , 270.sub.k. The second switching plane, i.e. plane 550.sub.2, feeds, through leads 570 formed of individual leads 570.sub.1, 570.sub.2, . . . , 570.sub.k, the second input (I.sub.2) of each of the 256 different output modules and so on with the last switching plane, i.e. plane 550.sub.m, feeding, through leads 580 formed of individual leads 580.sub.1, 580.sub.2, . . . 580.sub.k, the last input, I.sub.m, of every output module. Accordingly, the 256 outputs of every cross-point switching plane feed the same numerical input to every one of the 256 different output modules; each of the output modules, such as module 270.sub.1 is connected, such as through leads 565, to the same numerical output, such as output O.sub.1, of every cross-point switching plane. Each of the output modules routes incoming switched ATM cells to one of 32 separate output ports (O.sub.1, O.sub.2, . . . , O.sub.n) available on that module. Each of these ports is connected to a corresponding output line. Since each of the 256 different output modules feeds a group of 32 separate output lines, such as output lines 275.sub.1, 275.sub.2, . . . , 275.sub.k, switch fabric 250 services 8192 separate output ports (with all the lines connected thereto being collectively identified as output lines 275). Contention resolution unit 510, which will be discussed in detail below, is connected through multi-bit leads 515.sub.1, 515.sub.2, . . . , 515.sub.k which collectively form leads 515 to all of the input modules, specifically input modules 260.sub.1, 260.sub.2, . . . , 260.sub.k, respectively. Operationally speaking, ATM cells are routed through switch fabric 250 in a essentially a two-step process. First, each cell is routed based solely upon the L' portion of its prepended routing header through cross-point switching planes 550 to a particular output module without any regard to the specific output port on an output module to which that cell is destined. Second, that specific output module then routes that incoming cell, based upon the H portion of its prepended routing header, to the specific output port to which that cell is destined. Groups of cells, up to "k" (illustratively 256) in number, are simultaneously routed through each one of the cross-point switching planes with each of "m" (illustratively 32) such groups being routed on a staggered basis during each of "m" (illustratively 32) successive intervals that collectively form an STS-3c cell period, i.e. 2.83 .mu.sec. Specifically, each one of input modules 260 contains a single queue, such as queue 505, implemented with a shared memory containing a buffer having a size of 128 Kn cells. With respect to any one input module, such as module 260.sub.1, that module successively reads the current incoming ATM cell appearing at each of its inputs and deposits (writes) that cell into the next available location in the queue. This reading proceeds continuously in a round-robin fashion continually cycling through all the inputs in a circular manner. All thirty-two inputs are successively read in a phased fashion during each STS-3c cell period. For example, the first cell in the buffer may come from input I.sub.1 of that module, the next cell from input I.sub.2 and so on. In the event that an "idle" cell is present at any input, then the input module does not place anything into the appropriate location in the queue for that particular input. Between every two successive write operations, an input module reads a cell from the head of its internal queue ("HOQ"). For this specific HOQ cell, the input module first supplies the L' portion of its prepended routing header (i.e. which specifies the output module to which that cell is destined) to contention resolution unit 510. As such, during a read interval, all the input modules collectively supply simultaneous requests to the contention resolution unit to resolve contention for their current HOQ cells. Unit 510 determines whether any two (or more) ATM cells currently situated at the head of the queues in all the input modules are contending for the same output module. If so, the contention resolution unit determines, as specifically described in detail below and based upon: (a) the numerical top-down value of the input port on which that cell arrived, (b) the relative priority of all the HOQ cells and (c) fairness principles, the particular ATM cells that are situated at the HOQ positions which are to be currently and simultaneously routed from all the input modules, through the cross-point planes, to all the output modules. Once contention has been resolved, unit 510 provides the results, over leads 515, in the form of a single bit instruction back to each individual input module signifying whether that module should presently route or not route its HOQ cell onward through cross-point switching planes 550. Those cells that won arbitration are routed through a common, illustratively the first, cross-point switching plane, e.g. plane 550.sub.1. One cell, either active or idle, is routed through this plane to the first input (I.sub.1) of every output module. As such, a group of cells, up to "k" (illustratively 256) in number--if no contention whatsoever has occurred, are simultaneously routed through this plane to all the output modules. For those input modules that have won arbitration, a HOQ pointer is advanced by one to point to the next cell in each of their respective input queues; however, the HOQ pointer is not advanced for each of those input modules that has lost contention. Thereafter, all the input modules again send the L' portion of the routing header of the cells now located at the HOQ position in their internal queues to contention resolution unit 510. The winning cells that now result are routed to the next successive, e.g. the second, cross-point switching plane, e.g. plane 550.sub.2 which, in turn, simultaneously routes a second group of up to "k" ATM cells therethrough to all the output modules, and so on for each successive cross-point plane. Those cells that have previously lost arbitration for routing through one switching plane are generally accorded a higher favor (fairness) for purposes of resolving contention and being routed through the next successive switching plane than those cells that have just arrived at the HOQ position in their respective queues, thereby significantly and advantageously reducing the likelihood that head of queue blocking will occur within any input module. After winning ATM cells have been routed to the last cross-point plane, i.e. plane 550.sub.m, this process cyclically repeats with the first plane and so on. Once contention has been resolved for all the input modules, the winning ATM cells simultaneously supplied by those modules are routed through a common cross-point plane during the remainder of the STS-3c cell period. Thus, each of the input modules interleave read and write operations as successive input lines and outputs thereof are serviced. Inasmuch as all the input modules provide 256 cells at the end of each arbitration cycle and each separate switching plane requires essentially a full STS-3c cell period to route ATM cells therethrough, then, to fully occupy all the cross-point planes with switching activity, contention resolution unit 510 resolves contention at "m" times the STS-3c cell period, i.e. a complete arbitration cycle involving HOQ cells occurring at all the input modules is completely performed in 2.83/m .mu.sec. As such, all the cross-point planes operate on a time staggered (phased) basis throughout every STS-3c cell period with routing through each individual plane, e.g. plane 550.sub.1, being initiated for a group of cells 2.83/m .mu.sec earlier than at the point in time when the next successive plane, i.e. plane 550.sub.2, will commence routing the next successive group of cells therethrough. Furthermore, to substantially reduce the time interval needed to configure all the cross-points within switching planes 550 prior to routing a group of cells therethrough and thereby increase their effective switching bandwidth, the routing header of each cell applied to any input of a cross-point plane carries the output module address (L' value) for the next successive cell that is to be applied to that specific input. As such, once a cell header for a current ATM cell has been routed into a cross-point switching plane, the output module address in its routing header is used, in a manner described in detail below, to set the "future configuration" of the appropriate cross-points in the plane to properly switch the next successive cell that will appear on that input. As will be discussed below in conjunction with FIG. 9A, each individual cross-point circuit situated within each switching plane has an accompanying one-bit register that stores the "future configuration" of that circuit. After a group of ATM cells has been completely routed through a cross-point plane, a strobe pulse is applied to all the cross-point circuits within that plane to simultaneously set the switching configuration of all those circuits to that specified by their stored future configurations, thereby essentially instantaneously setting the entire plane to handle the next group of cells that will be switched therethrough. By storing the next successive switching configuration for each switching plane in advance of the occurrence of the actual corresponding ATM cells that are to be switched therethrough and then, immediately before the application of these cells to this plane, simultaneously setting all the cross-point circuits therein to reflect this configuration, this inventive technique can be viewed as providing cell address "look-ahead". By preserving the order of the cells in the internal queue in each input module in terms of sequential order of occurrence of the cells at every input port thereof as well as by sequentially reading and writing from the queue in the same order across all input lines to each input module, switch fabric 250 is able to switch ATM cells at several times the STS-3c rate. As can be appreciated, the signals that appear at the inputs of contention resolution unit 510 and at the inputs of each cross-point switching plane must be bit synchronized, to within an appropriate portion, for example .+-.30%, of a bit period. Any one of many well known techniques and associated circuits can be used to self-synchronize the bit-streams that appear at these inputs. For example, one such technique is described in R. J. Baumert et al, "A Monolithic 50-200 MHz CMOS Clock Recovery and Retiming Circuit", Proceedings of the IEEE 1989 Custom Integrated Circuits Conference, pages 14.5.1-14.5.4. Each of the output modules contains an internal queue, such as queue 595 situated within output module 270.sub.1, implemented with a shared memory having a buffer size of 128 Kn cells. The internal queue contains a separate logical queue (not specifically shown). To provide this functionality, the internal queue contains "n" separate logical queues, specifically linked lists, with separate pointers for the first (HOQ) and last entries therein. As each new ATM cell is routed to an input of an output module, specifically on a phased basis from one input to the next for this module, the output module simply reads the output port address, i.e. the "H" portion, of the routing header of that cell and deposits (writes) the bits that form that cell, specifically the data portion thereof, into the next available location in the logical queue for the specific output port to which that cell is destined. The last entry pointer for this logical queue is then appropriately updated to reflect this new entry. After all the inputs to an output module have been sequentially serviced, the output module successively reads the cell at the head of each logical queue and applies the bits that form that cell in bit-serial form to a corresponding output port. Reading begins with the first queue, sequentially proceeds to the n.sup.th queue and cyclically repeats, after a complete memory write cycle, in a round-robin fashion starting with the first queue and so on. The logic and memory contained within each output module is sufficiently fast to service every input and output of that module in one STS-3c cell period. As discussed above, the switching planes operate on a time staggered (phased) basis. FIG. 6 is a timing diagram of the inventive staggered routing and contention resolution operations that occur within switch fabric 250 for the "m" switching planes. A complete STS-3c cell period 610 is simply shown as T.sub.s in length. This time interval, specifically 2.83 .mu.sec, is that required to route a group of up to "k" simultaneously occurring cells through a single cross-point switching plane. The interval T.sub.c, illustratively designated by the numeral 620, is the time interval consumed for one contention resolution cycle, i.e. that required (2.83/m .mu.sec) by the contention resolution unit to resolve contention for the 256 cells simultaneously present at the head of the queues of all the input modules. The time scale, t, has been divided into intervals of T.sub.c seconds. As shown, each one of cross-point switching planes 550.sub.1, 550.sub.2, 550.sub.3, . . . , 550.sub.m routes a group of simultaneously occurring ATM cells therethrough during a respective corresponding time interval 630.sub.1, 630.sub.2, 630.sub.3, 630.sub.m, each of which is T.sub.s seconds in length, but which commences after a delay of T.sub.c seconds from the interval associated with the immediately preceding switching plane in sequence. Alternatively, the cross-point switching planes need not be operated on a time staggered basis. In this regard, contention could first be resolved for "m" (illustratively 32) successive groups of ATM cells. Once this occurs, all the winning cells from all such groups would be routed in parallel through the cross-point planes, with the winning cells in each group being simultaneously applied to the inputs of a different corresponding cross-point plane. As such, all the cross-point switching planes would receive synchronized cells and produce synchronized outputs. Now, while all 32 groups of cells are being routed through all the cross-point planes, contention could also be resolved for another 32 successive groups of cells, and so on. As such, the cross-point planes and the contention resolution unit would operate in parallel but not on a time staggered basis. In either case, if the contention resolution unit could resolve contention for a group of up to "k" simultaneously occurring ATM cells in less than 2.83/m .mu.sec, then more than 32 separate cross-point switching planes could be used, i.e. the value of "m" could be increased beyond 32. This, in turn, would permit more than 32 groups of ATM cells to be simultaneously routed, on either a staggered basis or not, through collectively all the cross-point planes thereby increasing the intermediate bandwidth of the entire packet switch. Furthermore, as discussed above, the routing header for each ATM cell that is applied to an input of a cross-point switching plane contains the output module address of the next successive ATM cell that will be applied to that specific input. FIG. 7 shows this specific relationship between such successive ATM cells and their associated prepended routing headers. For purposes of illustration, consider three successive ATM cells 710, 730 and 750 that are applied to a common input of a cross-point switching plane. The subscripts in this figure indicate the order of occurrence of the incoming ATM cells and their associated routing header portions. Cell 710 contains incoming ATM cell C.sub.1 designated by reference numeral 713 which has been applied to an input module and to which a routing header has been prepended. This routing header contains output module port address H.sub.1 in field 715 and, in field 717, the physical output module address, L.sub.2 ', for next successive cell 730. The correspondence between physical output port address L.sub.2 ' and cell 730 is symbolized by arrow 720. Cell 710 is followed by cell 730. This latter cell contains incoming ATM cell C.sub.2 designated by reference numeral 733 which has been applied to the same input module and to which a routing header has been prepended. This routing header contains output module port address H.sub.2 in field 735 and, in field 737, the physical output module address, L.sub.3 ', for next successive cell 750. The correspondence between the physical output port address L.sub.3 ' and next successive cell 750 is symbolized by arrow 740. This next successive cell contains incoming ATM cell C.sub.3 designated by reference numeral 753 which has been applied to the same input module and to which a routing header has been prepended. This routing header contains output module port address H.sub.3 in field 755 and, in field 757, the physical output module address, L.sub.4 ', which is associated with the next successive cell (not shown), and so on for all subsequent cells applied to this input of the cross-point switching plane. During switch start-up, the first ATM cell that is applied to each input of a cross-point plane merely contains a routing header that specifies an output port address for the next cell in sequence for that input followed by "idle" data thereafter. Storing the future configuration in advance of the corresponding cells, through use of the inventive cell address "look ahead" technique, significantly relaxes a relatively tight time constraint that would otherwise exist for reading the prepended routing header of each of the current cells and then setting the switch configuration therefor. As a result, the need to employ relatively costly high speed logic to read the prepended routing headers and set the configuration of all the cross-point circuits is advantageously eliminated. The switch can easily grow from a relatively small size by merely adding additional cross-point switching planes along with appropriate input and output modules. Inasmuch as the cost of installing "m" separate cross-point planes is expected to be significantly less than the cost of installing "k" separate input and output modules, it may be economically attractive to fabricate a switch containing a maximum number of cross-point switching planes but less than a full complement of input and output modules. In this scenario, some cross-point plane inputs would simply be idle. Then, over time, incremental numbers of input and output modules and accompanying interconnects (to previously unused cross-point switching plane inputs) would be successively added to the switch fabric to incrementally increase the capacity of the switch to keep pace with expanding market demand for B-ISDN service. Furthermore, it is likely that the cost of a full sized contention resolution unit would amount to an insignificant portion of the cost of the total switch fabric. Hence, such a unit could initially be economically incorporated into the switch fabric even if a number of the inputs to the unit were initially unused, particularly in view of the associated costs of expanding the cross-point planes at a later date. With this scenario, switch growth would simply be a linear function of the number of additional input and output module ports needed. Alternatively, a switch fabric could be fabricated with "k" input and output modules but with less than "m" switching planes, in which case some of the lines to the input and output modules would initially be idle. 2. Cross-point switching plane FIG. 8 is a high level block diagram of a typical cross-point switching plane, illustratively plane 550.sub.1, shown in FIG. 5. This diagram relies on fabricating plane 550.sub.1 using a 4-by-4 matrix of illustratively sixteen integrated 64-by-64 cross-point circuits, 800.sub.1, 800.sub.2, . . . , 800.sub.16, with each such integrated circuit being formed on a single chip. Input signals (I.sub.1, . . . , I.sub.k) which appear on leads 545 are routed in parallel from corresponding input modules by separate busses 805, 810, 815 and 820 to the inputs of each chip in each corresponding row in the matrix. The outputs produced by each column of chips in the matrix are applied in parallel through respective output busses 830, 835, 840 and 845 to output bus lines 560, which, in turn, collectively provide switched output signals (O.sub.1, . . . , O.sub.k) that feed respective output modules. Each integrated cross-point circuit employs tri-state output drivers in order to permit the outputs of these chips to be connected together in parallel. A strobe pulse is applied, via line 801, to all the cross-point circuits to signify the start of an ATM cell routing header. Although this architecture relies on using 64-by-64 cross-point circuits, the matrix can be readily reduced in each dimension to accommodate the use of 32-by-32 integrated cross-point circuits or alternatively expanded in each dimension to accommodate the use of integrated cross-point circuits that have a capacity greater than 64-by-64. The number of lines in each bus would necessarily change based upon the capacity of the specific integrated cross-point circuits that are to be used to form the matrix. In addition, the above-described values of parameters "n", "m" and "k" would also need to be changed accordingly. Through the use of the bus based architecture, the size of each cross-point plane can easily grow by merely adding additional cross-point switches in each dimension to that plane along with appropriate bus connections therefor. In this manner, a printed circuit board containing a cross-point switching plane could be installed with appropriate sockets to accommodate all such circuits but with a partial population of cross-point integrated circuits arranged in a relatively small matrix in some of these sockets. Circuits 800.sub.1, 800.sub.2, 800.sub.5 and 800.sub.6 could illustratively form such a matrix. Over time, as the need arose, additional cross-point integrated circuits could be added to the board, on a plug-in basis, to increase its switching capacity, as needed. Here, growth would exhibit a a squared dependency, i.e. a function of the difference in the squares of the total number of switching circuits that are required and the number of such circuits that are presently installed. FIG. 9A is a block diagram of one embodiment of a portion of a typical single self-routing cross-point circuit, illustratively circuit 800.sub.1 shown in FIG. 8, used within each cross-point plane in the inventive broadband ISDN switch. This particular embodiment sets all the cross-point switching elements in accordance with the inventive cell address "look ahead" technique, as described above. Although each cross-point circuit has been described as containing either, for example, 32-by-32 or 64-by-64 cross-point connections, in order to simplify this figure, it specifically shows a 4-by-4 cross-point circuit. Given the configuration of this circuit and the accompanying description, it will be readily apparent to anyone skilled in the art that larger cross-point circuits can be fabricated, within technological limits, by merely upwardly scaling the size of both the cross-point switching matrix and the ancillary support circuits to an appropriate level. As shown, this portion of cross-point circuit 800.sub.1 contains a square matrix of identical cross-point cells organized into rows and columns. Each such cell, of which cell 950 is typical, can assume either one of two states: closed or open. One-bit input signals are applied in parallel to all cells in a rows while one-bit outputs of all cells in a column are connected in parallel, specifically through a pre-charged bus scheme which is similar to the well known wired-OR configuration. If a cell, such as cell 950, is closed, then a signal appearing on its row input 805.sub.1 will be conducted through that cell to its columnar output 830.sub.1, and so on for all the other such cells. The state of all the cells, i.e. open or closed, is collectively referred to as the switch configuration. As noted above, each cell not only assumes its current configuration but also stores its future, specifically next, configuration. A one-bit register, such as register 957 is situated within each cell, such as cell 950, to store the future configuration. Each column of cross-point cells is connected, by vertical addressing lines 925, to column decoder 920 and, by horizontal addressing lines 935, to sequencer 930. A strobe pulse is connected through leads 915 and delay element 940 to an input of the sequencer. Incoming serial ATM cells are routed by input lines 805.sub.1, 805.sub.2, 805.sub.3 and 805.sub.4 to the inputs of corresponding rows of cross-point cells as well as to the inputs of shift registers 910.sub.1, 910.sub.2, 910.sub.3 and 910.sub.4. These shift registers collectively form shift registers 910. Any of the individual shift registers within registers 910 can be read in parallel through application of a suitable address by sequencer 930 to address leads 937. Each of these shift registers is sized to only hold the output module address (L' portion) of the prepended routing header. The outputs of the individual shift registers are connected in parallel and applied through leads 913 to an input of column decoder 920. Outgoing se |